公开(公告)号：US07268594B1

公开(公告)日：2007-09-11

申请号：US11128774

申请日：2005-05-13

申请人： Peter H. Alfke

发明人： Peter H. Alfke

IPC分类号： H03B21/00

CPC分类号： G06F1/025

摘要： An FPGA having a programmable frequency output is provided that achieves a (theoretical) M-times reduction in output jitter from a conventional direct digital synthesis (DDS) circuit, by running M accumulator circuits in parallel and combining the outputs in a time-staggered way. I Initially the frequency number N added into the accumulators is varied slightly for each accumulator by multiplying by a number, such as X/16 where X varies from 1 to 16 for each of 16 accumulator circuits. The accumulator circuits are further reconfigured so that the output of a register from a first accumulator provides feedback to the adder input in all of the accumulator circuits. The number of overflowing accumulator registers in a clock cycle will then indicate granularity spatially. To translate spatial granularity to time, a programmable delay circuit is connected to the output of each accumulator register.

摘要翻译： 提供具有可编程频率输出的FPGA，其通过并行运行M个累加器电路并且以时间交错方式组合输出，从而实现来自常规直接数字合成（DDS）电路的输出抖动的（理论）M次减少 。 首先，对于每个累加器，通过乘以一个数字，例如X / 16，其中，对于16个累加器电路中的每一个，X从1变化到16，对于每个累加器，添加到累加器中的频率数N稍微变化。 累加器电路进一步重新配置，使得来自第一累加器的寄存器的输出向所有累加器电路中的加法器输入提供反馈。 时钟周期中溢出的累加器寄存器的数量将在空间上指示粒度。 为了将空间粒度转换为时间，可编程延迟电路连接到每个累加器寄存器的输出。

公开(公告)号：US07020862B1

公开(公告)日：2006-03-28

申请号：US10803335

申请日：2004-03-17

申请人： Peter H. Alfke ,  Himanshu J. Verma

发明人： Peter H. Alfke ,  Himanshu J. Verma

IPC分类号： G06F17/50

CPC分类号： G01R31/318516 ,  G01R31/31725 ,  G01R31/318522

摘要： Described are systems and methods for quickly and accurately determining the set-up and hold-time requirements and clock-to-out delays associated with sequential logic elements on programmable logic devices. Programmable interconnect resources are configured to deliver signals to the data and clock terminals of each logic element under test. One or more variable delay circuits precisely place edges of the test signals on the elements of interest while a tester monitors the data clocked into the logic element to determine whether the logic element functions properly. This process is repeated for a number of selected delays.

摘要翻译： 描述了用于快速和准确地确定与可编程逻辑器件上的顺序逻辑元件相关联的建立和保持时间要求和时钟到输出延迟的系统和方法。 可编程互连资源被配置为将信号传送到被测试的每个逻辑元件的数据和时钟端子。 一个或多个可变延迟电路精确地将测试信号的边缘放置在感兴趣的元件上，同时测试器监视计时到逻辑元件中的数据，以确定逻辑元件是否正常工作。 对于多个选定的延迟重复该过程。

公开(公告)号：US06407612B1

公开(公告)日：2002-06-18

申请号：US09703127

申请日：2000-10-30

申请人： Peter H. Alfke

发明人： Peter H. Alfke

IPC分类号： H03K1716

CPC分类号： H03K3/037 ,  H03K3/013 ,  H03K3/0375

摘要： An input signal latching circuit for suppressing the effect of any ringing or other irregularities that occur within a specified time period after a transitional voltage level is reached, without significantly delaying the propagation of the input signal.

摘要翻译： 一种输入信号锁存电路，用于抑制在达到过渡电压电平之后的指定时间段内发生的任何振铃或其他不规则的影响，而不会显着延迟输入信号的传播。

公开(公告)号：US5969543A

公开(公告)日：1999-10-19

申请号：US790873

申请日：1997-02-03

申请人： Charles R. Erickson ,  Peter H. Alfke

发明人： Charles R. Erickson ,  Peter H. Alfke

IPC分类号： H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018585

摘要： An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., a keeper circuit), or follow the inverse of the input signal, or programmed permanently on, or programmed permanently off. The interface circuit can be used to provide a known and programmable output signal for an IC input (or internal line) that does not have a known driving source. By allowing this degree of flexibility, the input interface circuit of the present invention, under programmed control, generates an output signal with positive or negative feedback based on the input signal; or the input interface circuit provides a constant high or constant low signal output, or can oscillate or provide a high impedance response as output. In cases when the input pin (or internal line) is not being driven by a bus or source driver, the input interface provides a number of flexible configurations for supplying predetermined outputs. Within a programmable logic device, a separate input interface circuit is provided with each external pad (or internal line) that provides signals within the integrated circuit originating from associated input pins. The input interface contains two multiplexers which drive the pull-up and pull-down devices, each multiplexer being coupled to receive inputs from programmable memory cells and having a common control line.

摘要翻译： 一种用于逻辑器件的输入接口电路，其具有上拉和下拉器件的配置，用于基于未驱动的输入信号定义逻辑电平，其中上拉和下拉器件是独立且可单独编程的以跟随输入 信号（例如，保持器电路），或者跟随输入信号的倒数，或永久地编程或永久地编程。 接口电路可用于为不具有已知驱动源的IC输入（或内部线路）提供已知且可编程的输出信号。 通过允许这种程度的灵活性，本发明的输入接口电路在编程控制下，基于输入信号产生具有正或负反馈的输出信号; 或者输入接口电路提供恒定的高或恒定的低信号输出，或者可以作为输出振荡或提供高阻抗响应。 在输入引脚（或内部线路）不被总线或源驱动器驱动的情况下，输入接口提供多个用于提供预定输出的灵活配置。 在可编程逻辑器件内，提供单独的输入接口电路，每个外部焊盘（或内部线）提供来自相关输入引脚的集成电路内的信号。 输入接口包含驱动上拉和下拉器件的两个多路复用器，每个复用器被耦合以从可编程存储器单元接收输入并具有公共控制线。

公开(公告)号：US07227387B1

公开(公告)日：2007-06-05

申请号：US11128775

申请日：2005-05-13

申请人： Peter H. Alfke

发明人： Peter H. Alfke

IPC分类号： H03K5/22

CPC分类号： H03K5/26

摘要： A pulse width measurement system is provided with components in an FPGA so that pulse widths can be measured that are smaller than the frequency limits of the FPGA system clock. For the measurement, an incoming pulse is fed into the FPGA to many (e.g. 32) I/O inputs in parallel. Each parallel input is then provided to a programmable delay device with each delay configured to a different ascending delay value. The input transition time is then detected by converting the outputs from the delay devices into data indicating the timing information. In one embodiment the outputs of the delay devices address data stored in BRAMs for later processing in the FPGA to determine the timing information.

摘要翻译： 脉冲宽度测量系统在FPGA中提供组件，以便可以测量小于FPGA系统时钟频率限制的脉冲宽度。 对于测量，输入脉冲并行馈送到多个（例如32个）I / O输入到FPGA。 然后将每个并行输入提供给可编程延迟器件，其中每个延迟被配置为不同的上升延迟值。 然后通过将来自延迟装置的输出转换为指示定时信息的数据来检测输入转换时间。 在一个实施例中，延迟装置的输出对存储在BRAM中的数据进行寻址，以便稍后在FPGA中进行处理以确定定时信息。

公开(公告)号：US06934198B1

公开(公告)日：2005-08-23

申请号：US10838957

申请日：2004-05-04

申请人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

发明人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

IPC分类号： G06F5/14 ,  G11C7/00

CPC分类号： G06F5/14 ,  G06F2205/102 ,  G06F2205/126

摘要： An integrated circuit having an embedded first-in, first-out (“FIFO”) memory system uses an embedded block random access memory (“BRAM”). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a first pointer address, and the sum is converted to a first gray code value. The first gray code value is compared to a second gray code value that represents a second pointer address. If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY) in the correct clock domain.

摘要翻译： 具有嵌入式先进先出（“FIFO”）存储器系统的集成电路使用嵌入式块随机存取存储器（“BRAM”）。 计数器在读和写时钟域都工作。 二进制加法器将第一选择的偏移值和第一指针地址相加，并将和转换为第一灰度代码值。 将第一灰度代码值与表示第二指针地址的第二灰度代码值进行比较。 如果第一灰度代码值等于第二灰度代码值，则将比较器的输出提供给在正确的时钟域中产生状态标志（例如ALMOST FULL或ALMOST EMPTY）的逻辑块。

公开(公告)号：US5758192A

公开(公告)日：1998-05-26

申请号：US541860

申请日：1995-10-10

申请人： Peter H. Alfke

发明人： Peter H. Alfke

IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F13/16 ,  G06F13/20

CPC分类号： G06F5/14 ,  G06F13/1673 ,  G06F2205/102

摘要： A structure and method for determining whether a first in, first out (FIFO) memory is empty or full when the read address of the memory equals the write address of the memory. The read and write addresses are individually incremented, each in a predetermined circular sequence. The circular sequence is divided at least three segments. Portions of the read and write addresses are encoded to indicate the segments in which the read and write addresses are located. These encoded address portions are decoded to determine the relative segment positions of the read and write addresses. If the read address is in the segment prior to the write address, a DIRECTION signal is set to a first state. If the write address is in the segment prior to the read address, the DIRECTION signal is set to a second state. When the read address equals the write address, the state of the DIRECTION signal is used to determine whether the memory is empty or full. If the DIRECTION signal is in the first state, the memory is empty. If the DIRECTION signal is in the second state, the memory is full.

摘要翻译： 当存储器的读取地址等于存储器的写入地址时，用于确定先入先出（FIFO）存储器是空还是满的结构和方法。 读取和写入地址分别以预定的循环序列递增。 循环序列至少划分三段。 对读取和写入地址的部分进行编码，以指示读取和写入地址所在的段。 这些编码地址部分被解码以确定读取和写入地址的相对段位置。 如果读地址在写地址之前的段中，则将DIRECTION信号设置为第一状态。 如果写入地址在读取地址之前的段中，则DIRECTION信号被设置为第二状态。 当读地址等于写地址时，DIRECTION信号的状态用于确定存储器是空还是满。 如果DIRECTION信号处于第一状态，则存储器为空。 如果DIRECTION信号处于第二状态，则存储器已满。

公开(公告)号：US5600271A

公开(公告)日：1997-02-04

申请号：US528580

申请日：1995-09-15

申请人： Charles R. Erickson ,  Peter H. Alfke

发明人： Charles R. Erickson ,  Peter H. Alfke

IPC分类号： H03K19/0185 ,  H03K19/084

CPC分类号： H03K19/018585

摘要： An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., a keeper circuit), or follow the inverse of the input signal, or programmed permanently on, or programmed permanently off. The interface circuit can be used to provide a known and programmable output signal for an IC input (or internal line) that does not have a known driving source. By allowing this degree of flexibility, the input interface circuit of the present invention, under programmed control, generates an output signal with positive or negative feedback based on the input signal; or the input interface circuit provides a constant high or constant low signal output, or can oscillate or provide a high impedance response as output. In cases when the input pin (or internal line) is not being driven by a bus or source driver, the input interface provides a number of flexible configurations for supplying predetermined outputs. Within a programmable logic device, a separate input interface circuit is provided with each external pad (or internal line) that provides signals within the integrated circuit originating from associated input pins.

摘要翻译： 一种用于逻辑器件的输入接口电路，其具有上拉和下拉器件的配置，用于基于未驱动的输入信号定义逻辑电平，其中上拉和下拉器件是独立且可单独编程的以跟随输入 信号（例如，保持器电路），或者跟随输入信号的倒数，或永久地编程或永久地编程。 接口电路可用于为不具有已知驱动源的IC输入（或内部线路）提供已知且可编程的输出信号。 通过允许这种程度的灵活性，本发明的输入接口电路在编程控制下，基于输入信号产生具有正或负反馈的输出信号; 或者输入接口电路提供恒定的高或恒定的低信号输出，或者可以作为输出振荡或提供高阻抗响应。 在输入引脚（或内部线路）不被总线或源驱动器驱动的情况下，输入接口提供多个用于提供预定输出的灵活配置。 在可编程逻辑器件内，提供单独的输入接口电路，每个外部焊盘（或内部线）提供来自相关输入引脚的集成电路内的信号。

公开(公告)号：US4084082A

公开(公告)日：1978-04-11

申请号：US731242

申请日：1976-10-12

申请人： Peter H. Alfke

发明人： Peter H. Alfke

IPC分类号： H03K23/66 ,  H03K21/36

CPC分类号： H03K23/667

摘要： A programmable counter is described having three cascaded counters, the first one of which is a dual modulus prescaler. The second counter is a resettable binary counter which is fed information from a programmable read-only memory as to the numbers of times the prescaler divisions are to be repeated. The third counter is a binary counter which further divides the frequency and controls the repetition numbers delivered by the programmable read-only memory to the presettable binary counter.

摘要翻译： 描述了具有三个级联计数器的可编程计数器，其中第一个是双模预分频器。 第二计数器是可复位二进制计数器，其从可编程只读存储器馈送关于预分频器分割重复次数的信息。 第三计数器是二进制计数器，其进一步分频并将可编程只读存储器传递的重复数控制到可预置的二进制计数器。

公开(公告)号：US4023116A

公开(公告)日：1977-05-10

申请号：US703394

申请日：1976-07-08

申请人： Peter H. Alfke ,  Charles H. Alford ,  Eric G. Breeze

发明人： Peter H. Alfke ,  Charles H. Alford ,  Eric G. Breeze

IPC分类号： H03L7/089 ,  H03L7/191 ,  H03B3/04

CPC分类号： H03L7/0891 ,  H03L7/191

摘要： A phase-locked loop frequency synthesizer is described not having the uncontrolled modulation of its output normally associated with such a synthesizer due to a detection dead band inherent in the phase/frequency comparator which is a principal part thereof. The frequency synthesizer includes, as is conventional, a reference oscillator and an oscillator for generating the synthesizer output. The comparator is also included as is conventional to detect unwanted deviations of the phase and frequency of the synthesizer output so they can be corrected. In order to compensate for the inability of the comparator to detect small unwanted deviations, a pulse generator is added to the synthesizer to apply what is, in effect, an intentional periodic phase error signal greater than the dead band difference. This causes the phase of the desired output to be corrected in a controlled manner which will prevent undesired frequency modulation of its output.

摘要翻译： 描述了由于作为其主要部分的相位/频率比较器中固有的检测死区，不具有与这种合成器正常相关联的其输出的不受控制的调制的锁相环频率合成器。 频率合成器如常规那样包括用于产生合成器输出的参考振荡器和振荡器。 比较器也被包括在常规中以检测合成器输出的相位和频率的不需要的偏差，使得它们可被校正。 为了补偿比较器无法检测到小的不必要的偏差，将脉冲发生器加到合成器上以应用实际上是大于死区差的有意周期性相位误差信号。 这导致所需输出的相位以受控的方式被校正，这将防止其输出的不期望的频率调制。