公开(公告)号：US06934198B1

公开(公告)日：2005-08-23

申请号：US10838957

申请日：2004-05-04

申请人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

发明人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

IPC分类号： G06F5/14 ,  G11C7/00

CPC分类号： G06F5/14 ,  G06F2205/102 ,  G06F2205/126

摘要： An integrated circuit having an embedded first-in, first-out (“FIFO”) memory system uses an embedded block random access memory (“BRAM”). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a first pointer address, and the sum is converted to a first gray code value. The first gray code value is compared to a second gray code value that represents a second pointer address. If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY) in the correct clock domain.

摘要翻译： 具有嵌入式先进先出（“FIFO”）存储器系统的集成电路使用嵌入式块随机存取存储器（“BRAM”）。 计数器在读和写时钟域都工作。 二进制加法器将第一选择的偏移值和第一指针地址相加，并将和转换为第一灰度代码值。 将第一灰度代码值与表示第二指针地址的第二灰度代码值进行比较。 如果第一灰度代码值等于第二灰度代码值，则将比较器的输出提供给在正确的时钟域中产生状态标志（例如ALMOST FULL或ALMOST EMPTY）的逻辑块。

公开(公告)号：US07254677B1

公开(公告)日：2007-08-07

申请号：US10839402

申请日：2004-05-04

申请人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

发明人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

IPC分类号： G06F12/00

CPC分类号： G06F5/10

摘要： A first-in, first-out (“FIFO”) memory system embedded in a programmable logic device has an embedded FIFO memory array coupled to an output register. If the embedded FIFO memory is empty, the first word written to the FIFO memory system is pre-fetched to the output register. A first-word detection circuit asserts a DATA VALID signal if the first word is available to be read from the output register when READ ENABLE is asserted. In an alternative embodiment, the first word is pre-fetched to the output of the output register and is available to be read before READ ENABLE is asserted.

摘要翻译： 嵌入在可编程逻辑器件中的先进先出（“FIFO”）存储器系统具有耦合到输出寄存器的嵌入式FIFO存储器阵列。 如果嵌入式FIFO存储器为空，则写入FIFO存储器系统的第一个字被预取到输出寄存器。 如果在启用READ ENABLE时，如果第一个字可用于从输出寄存器读取，则第一个字检测电路会断言DATA VALID信号。 在替代实施例中，第一个字被预取到输出寄存器的输出，并且可以在READ ENABLE被声明之前被读取。

公开(公告)号：US06956776B1

公开(公告)日：2005-10-18

申请号：US10839201

申请日：2004-05-04

申请人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

发明人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

IPC分类号： G06F5/14 ,  G11C7/00

CPC分类号： G06F5/14 ,  G06F2205/102 ,  G06F2205/106 ,  G06F2205/126

摘要： A buffer memory status detection circuit has a binary logic gate (e.g. an OR gate) coupled to a comparator output signal that is asserted when a sum of a first address pointer of a FIFO memory array plus a first offset equals a second address pointer, and to a reset signal. Binary logic provides a binary output (i.e. “0” or “1”) in a first clock domain to two synchronization registers in series that convert the output to a second clock domain. An optional pipeline register improves timing of the output in the second clock domain, and is particularly desirable for use with high-speed clocks.

摘要翻译： 缓冲存储器状态检测电路具有耦合到比较器输出信号的二进制逻辑门（例如或门），当FIFO存储器阵列的第一地址指针和第一偏移的和等于第二地址指针时，比较器输出信号被置位;以及 到复位信号。 二进制逻辑将第一时钟域中的二进制输出（即“0”或“1”）提供给将输出转换为第二时钟域的串联的两个同步寄存器。 可选的流水线寄存器提高了第二个时钟域的输出时序，特别适用于高速时钟。

公开(公告)号：US06937172B1

公开(公告)日：2005-08-30

申请号：US10838965

申请日：2004-05-04

申请人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

发明人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

IPC分类号： G06F5/14 ,  H03K23/00 ,  H03M7/04

CPC分类号： G06F5/14 ,  G06F2205/102 ,  G06F2205/126 ,  H03K23/005

摘要： A system for gray-code counting in an integrated circuit such as a programmable logic device uses a binary adder coupled to a binary counter output and to a selected binary offset value. The binary adder provides a binary sum that is converted to a gray code value by a binary-to-gray converter. The gray code value represents the binary sum output.

摘要翻译： 在诸如可编程逻辑器件的集成电路中的用于灰度计数的系统使用耦合到二进制计数器输出和选择的二进制偏移值的二进制加法器。 二进制加法器提供通过二进制到灰色转换器转换为灰度值的二进制和。 灰色代码值表示二进制和输出。

公开(公告)号：US07161849B1

公开(公告)日：2007-01-09

申请号：US11140019

申请日：2005-05-27

申请人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

发明人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

IPC分类号： G11C7/10

CPC分类号： G06F5/14 ,  G06F2205/102 ,  G06F2205/126

摘要： An integrated circuit having an embedded first-in, first-out (“FIFO”) memory system uses an embedded block random access memory (“BRAM”). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a first pointer address, and the sum is converted to a first gray code value. The first gray code value is compared to a second gray code value that represents a second pointer address. If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY) in the correct clock domain.

摘要翻译： 具有嵌入式先进先出（“FIFO”）存储器系统的集成电路使用嵌入式块随机存取存储器（“BRAM”）。 计数器在读和写时钟域都工作。 二进制加法器将第一选择的偏移值和第一指针地址相加，并将和转换为第一灰度代码值。 将第一灰度代码值与表示第二指针地址的第二灰度代码值进行比较。 如果第一灰度代码值等于第二灰度代码值，则将比较器的输出提供给在正确的时钟域中产生状态标志（例如ALMOST FULL或ALMOST EMPTY）的逻辑块。

公开(公告)号：US07839181B1

公开(公告)日：2010-11-23

申请号：US12683581

申请日：2010-01-07

申请人： Peter H. Alfke

发明人： Peter H. Alfke

IPC分类号： G01R29/02

CPC分类号： H03K5/1252

摘要： Circuits and methods of suppressing signal glitches in an integrated circuit (IC). A glitch on a signal entering a clock buffer, for example, is prevented from propagating through the clock buffer. In some embodiments, a latch is added to an input clock path that detects a transition on the input signal, and then ignores any subsequent transitions for a time delta that is determined by a delay circuit. In some embodiments, a multiplexer circuit is used to select between the input clock signal and the output clock signal, with changes on the input clock signal not being passed through the multiplexer circuit unless the time delta has already elapsed. In some embodiments, the delay is programmable, pin-selectable, or self-adapting.

摘要翻译： 抑制集成电路（IC）中的信号毛刺的电路和方法。 例如，进入时钟缓冲器的信号的毛刺被阻止通过时钟缓冲器传播。 在一些实施例中，将锁存器添加到检测输入信号上的转换的输入时钟路径，然后忽略由延迟电路确定的时间增量的任何后续转换。 在一些实施例中，多路复用器电路用于在输入时钟信号和输出时钟信号之间进行选择，其中输入时钟信号的改变不会通过多路复用器电路，除非时间增量已经过去。 在一些实施例中，延迟是可编程的，引脚可选择的或自适应的。

公开(公告)号：US07291923B1

公开(公告)日：2007-11-06

申请号：US10627334

申请日：2003-07-24

申请人： Austin H. Lesea ,  Peter H. Alfke

发明人： Austin H. Lesea ,  Peter H. Alfke

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/532

CPC分类号： H01L23/5222 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an integrated circuit, a layer including a plurality of conductive wires is described. A first wire, having sidewalls, is tapered from a proximal end which has a first width to a distal end which has a second width, to reduce width from the first width to the second width, and the first wire also has a substantially vertical surface. A second wire, spaced apart from the first wire, also has a substantially vertical surface. The first wire and the second wire are each horizontally disposed along side each other forming a part of a sidewall capacitor between facing sidewalls. Capacitors are created between the first substantially vertical surface and the second substantially vertical surface, the capacitors are respectively associated with capacitances and with a plurality of loads, the plurality of loads is progressively reduced responsive to a progressive reduction of the capacitances as associated with the first wire taper.

摘要翻译： 在集成电路中，描述包括多根导线的层。 具有侧壁的第一线从具有第一宽度的第一宽度到具有第二宽度的远端的近端渐缩，以减小从第一宽度到第二宽度的宽度，并且第一线还具有基本垂直的表面 。 与第一线间隔开的第二线也具有基本垂直的表面。 第一线和第二线各自水平地彼此相对地设置，在相对的侧壁之间形成侧壁电容器的一部分。 电容器在第一基本上垂直的表面和第二基本上垂直的表面之间产生，电容器分别与电容和多个负载相关联，多个负载响应于与第一个相关联的电容的逐渐减小而逐渐减小 丝锥。

公开(公告)号：US07057413B1

公开(公告)日：2006-06-06

申请号：US10853419

申请日：2004-05-24

申请人： Steven P. Young ,  Peter H. Alfke ,  Trevor J. Bauer ,  Colm P. Fewer

发明人： Steven P. Young ,  Peter H. Alfke ,  Trevor J. Bauer ,  Colm P. Fewer

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H04Q3/0004 ,  H04Q3/521 ,  H04Q2213/13076

摘要： A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch, the input signals only carry crossbar switch data, and the connectivity is controlled by FPGA configuration data. The crossbar switch is implemented in two parts: a template of basic and constant routing to carry input signals through the switch array in one dimension and output signals from the array in another dimension, and a connectivity part controlled by a connectivity table or algorithm to generate partial reconfiguration bitstreams that determine which of the input signals is to be connected to which of the output signals.

摘要翻译： 描述了使用FPGA实现交叉开关的方法。 不是使用通过通用FPGA路由资源路由的信号来控制交叉开关的连接，而是输入信号只带有交叉开关数据，连接由FPGA配置数据控制。 交叉开关分两部分实现：基本和恒定路由的模板，通过一维的开关阵列传送输入信号，并在另一维度上输出阵列的信号，以及由连接表或算法控制的连接部分，以产生 部分重新配置比特流，其确定哪个输入信号要连接到哪个输出信号。

公开(公告)号：US06353341B1

公开(公告)日：2002-03-05

申请号：US09439844

申请日：1999-11-12

申请人： Austin H. Lesea ,  Peter H. Alfke ,  Jennifer Wong ,  Steven P. Young

发明人： Austin H. Lesea ,  Peter H. Alfke ,  Jennifer Wong ,  Steven P. Young

IPC分类号： G01R2902

CPC分类号： G01R31/31922 ,  G01R31/31937

摘要： A clock signal is monitored to detect a transition from a first logic state to a second logic state. Once this transition is detected, subsequent transitions of the clock signal are ignored for a predetermined time period during which signal interference is most significant. After lapse of the predetermined time period, the clock signal is again monitored to detect subsequent state transitions. In some embodiments, the clock signal is delayed using a delay circuit to produce a delayed clock signal which is used to force the clock signal to the second logic state for a predetermined time period. In one embodiment, the predetermined time period is user-selectable via one or more selectable taps on the delay circuit.

摘要翻译： 监视时钟信号以检测从第一逻辑状态到第二逻辑状态的转变。 一旦检测到该转变，则在时间信号的后续转换在信号干扰最显着的预定时间段期间被忽略。 在经过预定时间段之后，再次监视时钟信号以检测随后的状态转换。 在一些实施例中，使用延迟电路来延迟时钟信号以产生延迟的时钟信号，该延迟时钟信号用于将时钟信号强制到第二逻辑状态达预定时间段。 在一个实施例中，通过延迟电路上的一个或多个可选择的抽头，预定时间段是用户可选择的。

公开(公告)号：US08265902B1

公开(公告)日：2012-09-11

申请号：US12544437

申请日：2009-08-20

申请人： Noel J. Brady ,  Lionel Barker ,  Peter H. Alfke

发明人： Noel J. Brady ,  Lionel Barker ,  Peter H. Alfke

IPC分类号： G04F1/00

CPC分类号： G04F10/005

摘要： A circuit measures a time interval between a first event and a second event. One or more activity inputs receive a respective signal indicating the first and second events. For each activity input, a respective high-speed serial receiver includes a sampling circuit and a deserializer. The sampling circuit generates sample bits from sampling the respective signal at active edges of a clock signal. The deserializer converts the sample bits into a sequence of parallel data words. The sample bits undergo a first change in response to the first event and a second change in response to the second event. An arithmetic circuit receives the sequence of parallel data words from the respective high-speed serial receiver. The arithmetic circuit determines a number of the sample bits between the first and second changes in the sequence of parallel data words. The number measures the time interval between the first and second events.

摘要翻译： 电路测量第一事件和第二事件之间的时间间隔。 一个或多个活动输入接收指示第一和第二事件的相应信号。 对于每个活动输入，相应的高速串行接收器包括采样电路和解串器。 采样电路通过对时钟信号的有效边沿处的相应信号进行采样来产生采样位。 解串器将采样位转换为并行数据字序列。 样本比特响应于第一事件进行第一次改变，响应于第二事件进行第二次改变。 算术电路从各高速串行接收机接收并行数据字序列。 算术电路确定并行数据字序列中的第一和第二变化之间的样本比特数。 该数字测量第一和第二事件之间的时间间隔。