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公开(公告)号：US20120032275A1
公开(公告)日：2012-02-09
申请号：US12849390
申请日：2010-08-03
IPC分类号： H01L27/088 , H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/76805 , H01L21/76829 , H01L21/76895 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/41766 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.
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公开(公告)号：US08835232B2
公开(公告)日：2014-09-16
申请号：US13606694
申请日：2012-09-07
IPC分类号： H01L29/78
CPC分类号： H01L27/1203 , H01L21/823814 , H01L21/823842 , H01L29/42384 , H01L29/4908
摘要： A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.
摘要翻译： 在绝缘体上半导体（SOI）基板上形成一次性介质结构，使得一次性介质结构的所有物理暴露表面都是电介质表面。 半导体材料选择性地沉积在半导体表面上，同时抑制任何半导体材料在电介质表面上的沉积。 在形成至少一个栅极间隔物和源极和漏极区域之后，平坦化介电层被沉积并平坦化以物理暴露一次性介电结构的顶表面。 一次性介质结构被包括栅极电介质和栅极导体部分的替换栅极堆叠替代。 可以提供较低的外部电阻，而不会影响场效应晶体管器件的短沟道性能。
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13.发明授权Methods for obtaining gate stacks with tunable threshold voltage and scaling 有权用于获得具有可调阈值电压和缩放的栅极叠层的方法公开(公告)号：US07943458B2
公开(公告)日：2011-05-17
申请号：US12574318
申请日：2009-10-06
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： Methods of forming complementary metal oxide semiconductor (CMOS) structures with tunable threshold voltages are provided. The methods disclose a technique of obtaining selective placement of threshold voltage adjusting materials on a semiconductor substrate by using a block mask prior to deposition of the threshold voltage adjusting materials. The block mask is subsequently removed to obtain a patterned threshold voltage adjusting material on the semiconductor substrate. The methods are material independent and can be used in sequence for both nFET threshold voltage adjusting materials and pFET threshold voltage adjusting materials.
摘要翻译： 提供了形成具有可调阈值电压的互补金属氧化物半导体（CMOS）结构的方法。 该方法公开了一种在沉积阈值电压调节材料之前通过使用块掩模来获得阈值电压调节材料选择性放置在半导体衬底上的技术。 随后去除块掩模以在半导体衬底上获得图案化的阈值电压调节材料。 这些方法是材料独立的，并且可以顺序地用于nFET阈值电压调节材料和pFET阈值电压调节材料。
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公开(公告)号：US20130214358A1
公开(公告)日：2013-08-22
申请号：US13399040
申请日：2012-02-17
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/823814 , H01L21/823842 , H01L29/42384 , H01L29/4908
摘要： A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.
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15.发明申请SEMICONDUCTOR DEVICE INCLUDING MULTIPLE METAL SEMICONDUCTOR ALLOY REGION AND A GATE STRUCTURE COVERED BY A CONTINUOUS ENCAPSULATING LAYER 有权包括多个金属半导体合金区域的半导体器件和由连续封装层覆盖的栅极结构公开(公告)号：US20120326217A1
公开(公告)日：2012-12-27
申请号：US13604143
申请日：2012-09-05
IPC分类号： H01L29/78
CPC分类号： H01L29/78606 , H01L21/823835 , H01L29/4908 , H01L29/4966 , H01L29/66545 , H01L29/66772
摘要： A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device.
摘要翻译： 提供了一种形成半导体器件的方法，其在一些实施例中将栅极硅化物封装在连续封装材料中。 通过将栅极硅化物封装在封装材料中，本公开基本上消除了栅极结构与半导体器件的源极和漏极区域的互连之间的短路。
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16.发明授权Semiconductor device including multiple metal semiconductor alloy region and a gate structure covered by a continuous encapsulating layer 有权半导体器件包括多个金属半导体合金区域和由连续封装层覆盖的栅极结构公开(公告)号：US08901670B2
公开(公告)日：2014-12-02
申请号：US13604143
申请日：2012-09-05
IPC分类号： H01L21/02 , H01L29/786 , H01L29/49 , H01L21/8238 , H01L29/66
CPC分类号： H01L29/78606 , H01L21/823835 , H01L29/4908 , H01L29/4966 , H01L29/66545 , H01L29/66772
摘要： A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device.
摘要翻译： 提供了一种形成半导体器件的方法，其在一些实施例中将栅极硅化物封装在连续封装材料中。 通过将栅极硅化物封装在封装材料中，本公开基本上消除了栅极结构与半导体器件的源极和漏极区域的互连之间的短路。
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17.发明授权公开(公告)号：US08779515B2
公开(公告)日：2014-07-15
申请号：US13476364
申请日：2012-05-21
IPC分类号： H01L27/12
CPC分类号： H01L21/28 , H01L21/28008 , H01L21/76897 , H01L29/165 , H01L29/45 , H01L29/66545 , H01L29/66628
摘要： An aluminum-containing material is employed to form replacement gate electrodes. A contact-level dielectric material layer is formed above a planarization dielectric layer in which the replacement gate electrodes are embedded. At least one contact via cavity is formed through the contact-level dielectric layer. Any portion of the replacement gate electrodes that is physically exposed at a bottom of the at least one contact via cavity is vertically recessed. Physically exposed portions of the aluminum-containing material within the replacement gate electrodes are oxidized to form dielectric aluminum compound portions. Subsequently, each of the at least one active via cavity is further extended to an underlying active region, which can be a source region or a drain region. A contact via structure formed within each of the at least one active via cavity can be electrically isolated from the replacement gate electrodes by the dielectric aluminum compound portions.
摘要翻译： 采用含铝材料形成替代栅电极。 在平坦化介电层之上形成接触电介质材料层，其中嵌入有置换栅电极。 通过接触层电介质层形成至少一个接触通孔。 物理地暴露在至少一个接触通孔的底部的替代栅电极的任何部分是垂直凹陷的。 替代栅电极内的含铝材料的物理暴露部分被氧化以形成介电铝化合物部分。 随后，至少一个有源通孔腔中的每一个进一步延伸到下面的有源区，其可以是源区或漏区。 形成在所述至少一个有源通路腔的每一个内的接触通孔结构可以通过介电铝化合物部分与替换栅极电隔离。
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公开(公告)号：US20120205727A1
公开(公告)日：2012-08-16
申请号：US13025470
申请日：2011-02-11
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L29/78606 , H01L21/823835 , H01L29/4908 , H01L29/4966 , H01L29/66545 , H01L29/66772
摘要： A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device.
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19.发明申请DIFFERENTIAL STOICHIOMETRIES BY INFUSION THRU GCIB FOR MULTIPLE WORK FUNCTION METAL GATE CMOS 审中-公开用于多功能金属门CMOS的输入THRU GCIB的差分STOICHIOMETRIES公开(公告)号：US20120037999A1
公开(公告)日：2012-02-16
申请号：US12857108
申请日：2010-08-16
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/26566 , H01L21/28088 , H01L29/4966
摘要： A method of modulating the work function of a metal layer in a localized manner is provided. Metal gate electrodes having multiple work functions may then be formed from this metal layer. Although the metal layer and metal gate electrodes over both the nFET and pFET regions of the instant substrates are made from only a single metal, they exhibit different electrical performances. The variation of electrical performances is achieved by infusing stoichiometrically-altering atoms into the metal layer, from which the metal gate electrodes are made, via a Gas Cluster Ion Beam process. The resulting metal gate electrodes have the necessary threshold voltages for both nFET and pFET, and are ideal for use in CMOS devices.
摘要翻译： 提供了以局部方式调制金属层的功函数的方法。 然后可以由该金属层形成具有多个功函数的金属栅电极。 尽管本发明基板的nFET和pFET区域上的金属层和金属栅电极仅由单一金属制成，但它们表现出不同的电性能。 电气性能的变化通过将化学计量改变的原子通过气体聚簇离子束工艺注入到金属层中而形成金属栅电极来实现。 所得到的金属栅电极对于nFET和pFET均具有必要的阈值电压，并且是用于CMOS器件的理想选择。
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20.发明申请METHODS FOR OBTAINING GATE STACKS WITH TUNABLE THRESHOLD VOLTAGE AND SCALING 有权用于获得具有可调阈值电压和放大率的栅极堆叠的方法公开(公告)号：US20110081754A1
公开(公告)日：2011-04-07
申请号：US12574318
申请日：2009-10-06
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： Methods of forming complementary metal oxide semiconductor (CMOS) structures with tunable threshold voltages are provided. The methods disclose a technique of obtaining selective placement of threshold voltage adjusting materials on a semiconductor substrate by using a block mask prior to deposition of the threshold voltage adjusting materials. The block mask is subsequently removed to obtain a patterned threshold voltage adjusting material on the semiconductor substrate. The methods are material independent and can be used in sequence for both nFET threshold voltage adjusting materials and pFET threshold voltage adjusting materials.
摘要翻译： 提供了形成具有可调阈值电压的互补金属氧化物半导体（CMOS）结构的方法。 该方法公开了一种在沉积阈值电压调节材料之前通过使用块掩模来获得阈值电压调节材料选择性放置在半导体衬底上的技术。 随后去除块掩模以在半导体衬底上获得图案化的阈值电压调节材料。 这些方法是材料独立的，并且可以顺序地用于nFET阈值电压调节材料和pFET阈值电压调节材料。
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