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    Robust isolation for thin-box ETSOI MOSFETS
    2.
    发明授权
    Robust isolation for thin-box ETSOI MOSFETS 有权
    薄型ETSOI MOSFET的强大隔离性

    公开(公告)号：US08927387B2

    公开(公告)日：2015-01-06

    申请号：US13442168

    申请日：2012-04-09

    Applicant: Kangguo Cheng ,  Bruce B Doris ,  Balasubramanian S Haran ,  Sanjay Mehta ,  Stefan Schmitz

    Inventor： Kangguo Cheng ,  Bruce B Doris ,  Balasubramanian S Haran ,  Sanjay Mehta ,  Stefan Schmitz

    IPC: H01L27/088 ,  H01L21/336 ,  H01L21/762

    CPC classification number: H01L21/84 ,  H01L21/76283 ,  H01L27/1203

    Abstract: A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.

    Abstract translation: 薄型BOX ETSOI器件，具有强大的隔离性和制造方法。 该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层，其中第一半导体层具有10nm或更小的厚度。 该过程继续蚀刻到晶片中的浅沟槽，部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。 在间隔物形成之后，该过程继续蚀刻直接在第一间隔物下面和之间的区域，暴露第一间隔物的下侧，形成覆盖第一间隔物的所有暴露部分的第二间隔区，其中除去氧化垫层， 第一半导体晶片上的栅极结构。

    MOSFET including asymmetric source and drain regions
    3.
    发明授权
    MOSFET including asymmetric source and drain regions 失效
    MOSFET包括不对称的源极和漏极区域

    公开(公告)号：US08772874B2

    公开(公告)日：2014-07-08

    申请号：US13216554

    申请日：2011-08-24

    Applicant: Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66803 ,  H01L29/785

    Abstract: At least one drain-side surfaces of a field effect transistor (FET) structure, which can be a structure for a planar FET or a fin FET, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface. A raised epitaxial source region has a greater thickness than a raised epitaxial drain region, thereby providing an asymmetric FET having lesser source-side external resistance than drain-side external resistance, and having lesser drain-side overlap capacitance than source-side overlap capacitance.

    Abstract translation: 作为平面FET或鳍式FET的结构的场效应晶体管（FET）结构的至少一个漏极侧表面在结构上被惰性或电活性掺杂剂的成角度的离子注入损坏，而至少一个 保护晶体管的源极侧表面不被栅极堆叠和栅极间隔物的注入。 半导体材料的外延生长在至少一个结构损坏的漏极侧表面上延迟，而外延生长在至少一个源极侧表面上没有延迟。 凸起的外延源区域具有比凸起的外延漏极区域更大的厚度，从而提供具有比漏极侧外部电阻更小的源极侧外部电阻并且具有比源极重叠电容更少的漏极侧重叠电容的非对称FET。

    SOI DEVICE WITH EMBEDDED LINER IN BOX LAYER TO LIMIT STI RECESS
    4.
    发明申请
    SOI DEVICE WITH EMBEDDED LINER IN BOX LAYER TO LIMIT STI RECESS 有权
    具有嵌入式衬垫的SOI器件限制STI感染

    公开(公告)号：US20140070357A1

    公开(公告)日：2014-03-13

    申请号：US13611182

    申请日：2012-09-12

    Applicant: Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth

    Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth

    IPC: H01L29/06 ,  H01L21/762

    CPC classification number: H01L27/1203 ,  H01L21/31144 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66772 ,  H01L29/78654

    Abstract: A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.

    Abstract translation: 具有隔离区域的半导体基板及其形成方法。 该方法包括以下步骤：提供具有衬底层，掩埋氧化物（BOX），绝缘体上硅（SOI）层，衬垫氧化物层和衬垫氮化物层的衬底，形成浅沟槽区，蚀刻衬垫 氧化层以形成耳朵并蚀刻BOX层以形成底切，在浅沟槽区域上沉积衬垫，在浅沟槽区域的表面上沉积软掩模，填充浅沟槽区域，蚀刻软掩模，使得它 凹陷到BOX层的顶部，在某些区域蚀刻衬垫，去除软掩模，以及填充和抛光浅沟槽区域。 当触点不对准时，衬垫防止半导体器件的短路。

    Semiconductor substrate with transistors having different threshold voltages
    5.
    发明授权
    Semiconductor substrate with transistors having different threshold voltages 失效
    具有不同阈值电压的晶体管的半导体衬底

    公开(公告)号：US08642415B2

    公开(公告)日：2014-02-04

    申请号：US13487511

    申请日：2012-06-04

    Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

    Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

    IPC: H01L21/8238

    CPC classification number: H01L27/1203 ,  H01L21/84

    Abstract: A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.

    Abstract translation: 公开了一种制造半导体集成电路的方法。 该方法包括在半导体衬底上形成第一场效应晶体管（FET）器件和第二FET器件。 该方法包括在第一高度上外延生长用于第一FET器件的升高的源极/漏极（RSD）结构。 该方法包括在第二高度上外延生长用于第二FET器件的升高的源极/漏极（RSD）结构。 第二高度大于第一高度，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

    Low resistance source and drain extensions for ETSOI
    6.
    发明授权
    Low resistance source and drain extensions for ETSOI 失效
    用于ETSOI的低电阻源和漏极扩展

    公开(公告)号：US08614486B2

    公开(公告)日：2013-12-24

    申请号：US13605260

    申请日：2012-09-06

    Applicant: Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

    Inventor： Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

    IPC: H01L29/02 ,  H01L21/02

    CPC classification number: H01L29/66772 ,  H01L29/6653 ,  H01L29/78621

    Abstract: A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

    Abstract translation: 在通过各向异性蚀刻共形介电层形成第一栅极间隔物之后对栅极电介质进行构图，以最小化过蚀刻到半导体层中。 在一个实施例中，执行选择性外延以顺序地形成凸起的外延半导体部分，一次性栅极间隔物和升高的源极和漏极区域。 去除一次性栅极间隔物，并将离子注入进行到隆起的外延半导体部分的暴露部分中以形成源极和漏极延伸区域。 在另一个实施例中，用于源极和漏极延伸形成的离子注入在形成第一栅极间隔物的各向异性蚀刻之前通过保形介电层进行。 升高的外延半导体部分或构象介电层的存在防止了源极和漏极延伸区域中的半导体材料的完全非晶化，从而使结晶源极和漏极延伸区域再生长。

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