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1.发明授权Methods for obtaining gate stacks with tunable threshold voltage and scaling 有权用于获得具有可调阈值电压和缩放的栅极叠层的方法公开(公告)号：US07943458B2
公开(公告)日：2011-05-17
申请号：US12574318
申请日：2009-10-06
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： Methods of forming complementary metal oxide semiconductor (CMOS) structures with tunable threshold voltages are provided. The methods disclose a technique of obtaining selective placement of threshold voltage adjusting materials on a semiconductor substrate by using a block mask prior to deposition of the threshold voltage adjusting materials. The block mask is subsequently removed to obtain a patterned threshold voltage adjusting material on the semiconductor substrate. The methods are material independent and can be used in sequence for both nFET threshold voltage adjusting materials and pFET threshold voltage adjusting materials.
摘要翻译： 提供了形成具有可调阈值电压的互补金属氧化物半导体（CMOS）结构的方法。 该方法公开了一种在沉积阈值电压调节材料之前通过使用块掩模来获得阈值电压调节材料选择性放置在半导体衬底上的技术。 随后去除块掩模以在半导体衬底上获得图案化的阈值电压调节材料。 这些方法是材料独立的，并且可以顺序地用于nFET阈值电压调节材料和pFET阈值电压调节材料。
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2.发明申请METHODS FOR OBTAINING GATE STACKS WITH TUNABLE THRESHOLD VOLTAGE AND SCALING 有权用于获得具有可调阈值电压和放大率的栅极堆叠的方法公开(公告)号：US20110081754A1
公开(公告)日：2011-04-07
申请号：US12574318
申请日：2009-10-06
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： Methods of forming complementary metal oxide semiconductor (CMOS) structures with tunable threshold voltages are provided. The methods disclose a technique of obtaining selective placement of threshold voltage adjusting materials on a semiconductor substrate by using a block mask prior to deposition of the threshold voltage adjusting materials. The block mask is subsequently removed to obtain a patterned threshold voltage adjusting material on the semiconductor substrate. The methods are material independent and can be used in sequence for both nFET threshold voltage adjusting materials and pFET threshold voltage adjusting materials.
摘要翻译： 提供了形成具有可调阈值电压的互补金属氧化物半导体（CMOS）结构的方法。 该方法公开了一种在沉积阈值电压调节材料之前通过使用块掩模来获得阈值电压调节材料选择性放置在半导体衬底上的技术。 随后去除块掩模以在半导体衬底上获得图案化的阈值电压调节材料。 这些方法是材料独立的，并且可以顺序地用于nFET阈值电压调节材料和pFET阈值电压调节材料。
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公开(公告)号：US08735243B2
公开(公告)日：2014-05-27
申请号：US11834641
申请日：2007-08-06
申请人： Matthew W. Copel , Bruce B. Doris , Vijay Narayanan , Yun-Yu Wang
发明人： Matthew W. Copel , Bruce B. Doris , Vijay Narayanan , Yun-Yu Wang
IPC分类号： H01L21/8238 , H01L21/335 , H01L21/336 , H01L21/8234 , H01L29/51 , H01L21/28
CPC分类号： H01L29/513 , H01L21/28026 , H01L21/28229 , H01L21/823857 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/7833
摘要： A method for fabricating an FET device is disclosed. The FET device has a gate insulator with a high-k dielectric portion, and a threshold modifying material. The method introduces a stabilizing material into the gate insulator in order to hinder one or more metals from the threshold modifying material to penetrate across the high-k portion of the gate insulator. The introduction of the stabilizing material may involve disposing a stabilizing agent over a layer which contains an oxide of the one or more metals. A stabilizing material may also be incorporated into the high-k dielectric. Application of the method may lead to FET devices with unique gate insulator structures.
摘要翻译： 公开了一种用于制造FET器件的方法。 FET器件具有具有高k电介质部分的栅极绝缘体和阈值修饰材料。 该方法将稳定材料引入栅极绝缘体中，以便阻止来自阈值修饰材料的一种或多种金属穿过栅极绝缘体的高k部分。 稳定材料的引入可以包括在包含一种或多种金属的氧化物的层上设置稳定剂。 稳定材料也可以并入高k电介质中。 该方法的应用可能导致具有独特栅极绝缘体结构的FET器件。
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4.发明授权Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics 有权在具有高k电介质的CMOS器件制造中实现势垒层的选择性实现以实现阈值电压控制公开(公告)号：US08193051B2
公开(公告)日：2012-06-05
申请号：US13047172
申请日：2011-03-14
申请人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.
摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。
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公开(公告)号：US08053772B2
公开(公告)日：2011-11-08
申请号：US12549297
申请日：2009-08-27
申请人： David B. Mitzi , Matthew W. Copel
发明人： David B. Mitzi , Matthew W. Copel
IPC分类号： H01L29/04
CPC分类号： C23C18/1295 , C23C18/1204 , C23C18/1225 , C23C18/14 , H01L29/66742 , H01L29/78681 , Y10T428/25 , Y10T428/30 , Y10T428/31507 , Y10T428/31678
摘要： A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.
摘要翻译： 一种沉积金属硫族化物膜的方法，包括以下步骤：使金属硫族化物的分离的肼鎓前体和其中具有增溶添加剂的溶剂接触以形成其络合物溶液; 将复合物的溶液施加到基底上以在基底上产生溶液的涂层; 从涂层中除去溶剂以在基材上产生复合物的膜; 然后使复合物的膜退火，以在衬底上产生金属硫族化物膜。 还提供了制备金属硫族化物的分离的肼鎓前体的方法以及使用金属硫属元素作为沟道层的薄膜场效应晶体管器件。
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公开(公告)号：US20110240932A1
公开(公告)日：2011-10-06
申请号：US13112356
申请日：2011-05-20
申请人： David B. Mitzi , Matthew W. Copel
发明人： David B. Mitzi , Matthew W. Copel
IPC分类号： H01B1/00
CPC分类号： C23C18/1295 , C23C18/1204 , C23C18/1225 , C23C18/14 , H01L29/66742 , H01L29/78681 , Y10T428/25 , Y10T428/30 , Y10T428/31507 , Y10T428/31678
摘要： A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.
摘要翻译： 一种沉积金属硫族化物膜的方法，包括以下步骤：使金属硫族化物的分离的肼鎓前体与其中具有增溶添加剂的溶剂接触以形成其络合物溶液; 将复合物的溶液施加到基底上以在基底上产生溶液的涂层; 从涂层中除去溶剂以在基材上产生复合物的膜; 然后使复合物的膜退火，以在衬底上产生金属硫族化物膜。 还提供了制备金属硫族化物的分离的肼鎓前体的方法以及使用金属硫属元素作为沟道层的薄膜场效应晶体管器件。
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公开(公告)号：US20100041907A1
公开(公告)日：2010-02-18
申请号：US12549297
申请日：2009-08-27
申请人： David B. Mitzi , Matthew W. Copel
发明人： David B. Mitzi , Matthew W. Copel
CPC分类号： C23C18/1295 , C23C18/1204 , C23C18/1225 , C23C18/14 , H01L29/66742 , H01L29/78681 , Y10T428/25 , Y10T428/30 , Y10T428/31507 , Y10T428/31678
摘要： A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.
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8.发明授权Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices 有权使用金属/金属氮化物双层作为自对准积极缩放的CMOS器件中的栅电极公开(公告)号：US07598545B2
公开(公告)日：2009-10-06
申请号：US11111592
申请日：2005-04-21
申请人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
发明人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
IPC分类号： H01L29/00
CPC分类号： H01L21/823842
摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
摘要翻译： 本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。 根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及 所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。 本发明还提供了制造这种CMOS结构的方法。
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9.发明申请STABILIZATION OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HAFNIUM OXIDE BASED SILICON TRANSISTORS FOR CMOS 审中-公开用于CMOS的基于氧化铝的硅晶体管中的平坦电压稳压和阈值电压稳定公开(公告)号：US20080258198A1
公开(公告)日：2008-10-23
申请号：US12166690
申请日：2008-07-02
申请人： Nestor A. Bojarczuk , Michael P. Chudzik , Matthew W. Copel , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk , Michael P. Chudzik , Matthew W. Copel , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L29/76
CPC分类号： H01L21/28167 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/517
摘要： The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising: a hafnium-based dielectric; a rare earth metal-containing layer located atop of, or within, said hafnium-based dielectric; an electrically conductive capping layer located above said hafnium-based dielectric; and a Si-containing conductor.
摘要翻译： 本发明提供一种金属堆叠结构，其稳定包括含Si导体和Hf基电介质的材料堆叠的平带电压和阈值电压。 本发明通过将含稀土金属的层引入材料堆中来稳定平带电压和阈值电压，其通过电负性差异将阈值电压的偏移引入期望的电压。 具体地说，本发明提供了一种金属叠层，包括：铪基电介质; 位于所述铪基电介质的顶部或内部的含稀土金属的层; 位于所述铪基电介质上方的导电覆盖层; 和含Si导体。
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公开(公告)号：US5628834A
公开(公告)日：1997-05-13
申请号：US438004
申请日：1995-05-09
申请人： Matthew W. Copel , Rudolf M. Tromp
发明人： Matthew W. Copel , Rudolf M. Tromp
IPC分类号： C30B23/02 , C30B25/02 , C30B25/18 , H01L21/203 , H01L29/165
CPC分类号： C30B23/02 , C30B25/02 , C30B25/18 , C30B29/06 , C30B29/08 , C30B29/52 , Y10S148/072 , Y10S148/097
摘要： The present invention broadly concerns layered structures of substantially-crystalline materials and processes for making such structures. More particularly, the invention concerns epitaxial growth of a substantially-crystalline layer of a first material on a substantially-crystalline second material different from the first material utilizing an approximately one monolayer thick monovalent surfactant element.
摘要翻译： 本发明广泛涉及基本结晶材料的层状结构和制造这种结构的方法。 更具体地，本发明涉及使用大约一个单层厚度的一价表面活性剂元件，在不同于第一材料的基本上为结晶的第二材料上的第一材料的基本晶体层的外延生长。
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