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公开(公告)号：US08835232B2
公开(公告)日：2014-09-16
申请号：US13606694
申请日：2012-09-07
IPC分类号： H01L29/78
CPC分类号： H01L27/1203 , H01L21/823814 , H01L21/823842 , H01L29/42384 , H01L29/4908
摘要： A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.
摘要翻译： 在绝缘体上半导体（SOI）基板上形成一次性介质结构，使得一次性介质结构的所有物理暴露表面都是电介质表面。 半导体材料选择性地沉积在半导体表面上，同时抑制任何半导体材料在电介质表面上的沉积。 在形成至少一个栅极间隔物和源极和漏极区域之后，平坦化介电层被沉积并平坦化以物理暴露一次性介电结构的顶表面。 一次性介质结构被包括栅极电介质和栅极导体部分的替换栅极堆叠替代。 可以提供较低的外部电阻，而不会影响场效应晶体管器件的短沟道性能。
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公开(公告)号：US08614486B2
公开(公告)日：2013-12-24
申请号：US13605260
申请日：2012-09-06
CPC分类号： H01L29/66772 , H01L29/6653 , H01L29/78621
摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.
摘要翻译： 在通过各向异性蚀刻共形介电层形成第一栅极间隔物之后对栅极电介质进行构图，以最小化过蚀刻到半导体层中。 在一个实施例中，执行选择性外延以顺序地形成凸起的外延半导体部分，一次性栅极间隔物和升高的源极和漏极区域。 去除一次性栅极间隔物，并将离子注入进行到隆起的外延半导体部分的暴露部分中以形成源极和漏极延伸区域。 在另一个实施例中，用于源极和漏极延伸形成的离子注入在形成第一栅极间隔物的各向异性蚀刻之前通过保形介电层进行。 升高的外延半导体部分或构象介电层的存在防止了源极和漏极延伸区域中的半导体材料的完全非晶化，从而使结晶源极和漏极延伸区域再生长。
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3.发明授权Methods for obtaining gate stacks with tunable threshold voltage and scaling 有权用于获得具有可调阈值电压和缩放的栅极叠层的方法公开(公告)号：US07943458B2
公开(公告)日：2011-05-17
申请号：US12574318
申请日：2009-10-06
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： Methods of forming complementary metal oxide semiconductor (CMOS) structures with tunable threshold voltages are provided. The methods disclose a technique of obtaining selective placement of threshold voltage adjusting materials on a semiconductor substrate by using a block mask prior to deposition of the threshold voltage adjusting materials. The block mask is subsequently removed to obtain a patterned threshold voltage adjusting material on the semiconductor substrate. The methods are material independent and can be used in sequence for both nFET threshold voltage adjusting materials and pFET threshold voltage adjusting materials.
摘要翻译： 提供了形成具有可调阈值电压的互补金属氧化物半导体（CMOS）结构的方法。 该方法公开了一种在沉积阈值电压调节材料之前通过使用块掩模来获得阈值电压调节材料选择性放置在半导体衬底上的技术。 随后去除块掩模以在半导体衬底上获得图案化的阈值电压调节材料。 这些方法是材料独立的，并且可以顺序地用于nFET阈值电压调节材料和pFET阈值电压调节材料。
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公开(公告)号：US20130214358A1
公开(公告)日：2013-08-22
申请号：US13399040
申请日：2012-02-17
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/823814 , H01L21/823842 , H01L29/42384 , H01L29/4908
摘要： A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.
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公开(公告)号：US08486778B2
公开(公告)日：2013-07-16
申请号：US13183666
申请日：2011-07-15
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/6653 , H01L29/78621
摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.
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6.发明申请SEMICONDUCTOR DEVICE INCLUDING MULTIPLE METAL SEMICONDUCTOR ALLOY REGION AND A GATE STRUCTURE COVERED BY A CONTINUOUS ENCAPSULATING LAYER 有权包括多个金属半导体合金区域的半导体器件和由连续封装层覆盖的栅极结构公开(公告)号：US20120326217A1
公开(公告)日：2012-12-27
申请号：US13604143
申请日：2012-09-05
IPC分类号： H01L29/78
CPC分类号： H01L29/78606 , H01L21/823835 , H01L29/4908 , H01L29/4966 , H01L29/66545 , H01L29/66772
摘要： A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device.
摘要翻译： 提供了一种形成半导体器件的方法，其在一些实施例中将栅极硅化物封装在连续封装材料中。 通过将栅极硅化物封装在封装材料中，本公开基本上消除了栅极结构与半导体器件的源极和漏极区域的互连之间的短路。
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7.发明授权公开(公告)号：US08394684B2
公开(公告)日：2013-03-12
申请号：US12841408
申请日：2010-07-22
IPC分类号： H01L21/84
CPC分类号： H01L27/0886 , H01L21/82 , H01L29/66795 , H01L29/7847 , H01L29/785
摘要： Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed.
摘要翻译： 公开了一种技术来将外部应力施加到源极/漏极半导体鳍状物侧壁区域上并将其锁定到半导体鳍片上，然后释放侧壁以用于随后的盐化和接触形成。 特别地，本公开提供了一种方法，其中半导体的选定部分经受非晶化离子注入，其相对于在栅极堆叠下面的半导体鳍片的部分使半导体鳍片的选定部分的晶体结构脱落， 用各种衬垫封装。 形成至少一个应力衬垫，然后通过进行应力闭锁退火而发生应力记忆。 在该退火期间，发生错位取向的晶体结构的再结晶。 去除至少一个应力衬垫，然后执行源极/漏极区域中的半导体鳍片的合并。
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8.发明授权Semiconductor device including multiple metal semiconductor alloy region and a gate structure covered by a continuous encapsulating layer 有权半导体器件包括多个金属半导体合金区域和由连续封装层覆盖的栅极结构公开(公告)号：US08901670B2
公开(公告)日：2014-12-02
申请号：US13604143
申请日：2012-09-05
IPC分类号： H01L21/02 , H01L29/786 , H01L29/49 , H01L21/8238 , H01L29/66
CPC分类号： H01L29/78606 , H01L21/823835 , H01L29/4908 , H01L29/4966 , H01L29/66545 , H01L29/66772
摘要： A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device.
摘要翻译： 提供了一种形成半导体器件的方法，其在一些实施例中将栅极硅化物封装在连续封装材料中。 通过将栅极硅化物封装在封装材料中，本公开基本上消除了栅极结构与半导体器件的源极和漏极区域的互连之间的短路。
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9.发明授权公开(公告)号：US08779515B2
公开(公告)日：2014-07-15
申请号：US13476364
申请日：2012-05-21
IPC分类号： H01L27/12
CPC分类号： H01L21/28 , H01L21/28008 , H01L21/76897 , H01L29/165 , H01L29/45 , H01L29/66545 , H01L29/66628
摘要： An aluminum-containing material is employed to form replacement gate electrodes. A contact-level dielectric material layer is formed above a planarization dielectric layer in which the replacement gate electrodes are embedded. At least one contact via cavity is formed through the contact-level dielectric layer. Any portion of the replacement gate electrodes that is physically exposed at a bottom of the at least one contact via cavity is vertically recessed. Physically exposed portions of the aluminum-containing material within the replacement gate electrodes are oxidized to form dielectric aluminum compound portions. Subsequently, each of the at least one active via cavity is further extended to an underlying active region, which can be a source region or a drain region. A contact via structure formed within each of the at least one active via cavity can be electrically isolated from the replacement gate electrodes by the dielectric aluminum compound portions.
摘要翻译： 采用含铝材料形成替代栅电极。 在平坦化介电层之上形成接触电介质材料层，其中嵌入有置换栅电极。 通过接触层电介质层形成至少一个接触通孔。 物理地暴露在至少一个接触通孔的底部的替代栅电极的任何部分是垂直凹陷的。 替代栅电极内的含铝材料的物理暴露部分被氧化以形成介电铝化合物部分。 随后，至少一个有源通孔腔中的每一个进一步延伸到下面的有源区，其可以是源区或漏区。 形成在所述至少一个有源通路腔的每一个内的接触通孔结构可以通过介电铝化合物部分与替换栅极电隔离。
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公开(公告)号：US20120205727A1
公开(公告)日：2012-08-16
申请号：US13025470
申请日：2011-02-11
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L29/78606 , H01L21/823835 , H01L29/4908 , H01L29/4966 , H01L29/66545 , H01L29/66772
摘要： A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device.
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