公开(公告)号：US06383925B1

公开(公告)日：2002-05-07

申请号：US09497850

申请日：2000-02-04

Applicant: Minh Van Ngo ,  Lu You ,  Robert A. Huertas ,  Ercan Adem

Inventor： Minh Van Ngo ,  Lu You ,  Robert A. Huertas ,  Ercan Adem

IPC: H01L2144

CPC classification number: H01L21/76838 ,  H01L21/76834 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member, after CMP, in a reaction chamber with a plasma containing ammonia and nitrogen for a brief period of time to reduce the surface oxide and then introducing silane into the reaction chamber to deposit the barrier layer, e.g., silicon nitride, under high density plasma conditions in the presence of nitrogen. The presence of nitrogen during plasma oxide layer reduction and plasma barrier layer deposition significantly improves adhesion of the barrier layer to the Cu or Cu alloy surface.

Abstract translation: 通过在具有氨和氮气的等离子体的反应室中处理Cu或Cu合金互连构件的CMP暴露表面之后，通过将Cu或Cu合金互连构件的阻挡层或覆盖层的粘合性显着提高， 一段时间以减少表面氧化物，然后将硅烷引入反应室，以在氮气存在下在高密度等离子体条件下沉积阻挡层，例如氮化硅。 在等离子体氧化物层还原和等离子体阻挡层沉积期间氮的存在显着提高了阻挡层对Cu或Cu合金表面的粘附性。

公开(公告)号：US07468296B1

公开(公告)日：2008-12-23

申请号：US11290787

申请日：2005-11-30

Applicant: Ercan Adem ,  Matthew Buynoski ,  Robert Chiu ,  Bryan Choo ,  Calvin Gabriel ,  Joong Jeon ,  David Matsumoto ,  Jeffrey Shields ,  Bhanwar Singh ,  Winny Stockwell ,  Wen Yu

Inventor： Ercan Adem ,  Matthew Buynoski ,  Robert Chiu ,  Bryan Choo ,  Calvin Gabriel ,  Joong Jeon ,  David Matsumoto ,  Jeffrey Shields ,  Bhanwar Singh ,  Winny Stockwell ,  Wen Yu

IPC: H01L21/8234 ,  H01L27/10

CPC classification number: H01L27/1021

Abstract: In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.

Abstract translation: 在制造电子结构时，提供基板，并且在基板上设置第一阻挡层。 锗薄膜二极管设置在第一阻挡层上，第二阻挡层设置在锗薄膜二极管上。 存储器件设置在第二阻挡层上并连接到第二阻挡层。

公开(公告)号：US07361586B2

公开(公告)日：2008-04-22

申请号：US11173244

申请日：2005-07-01

Applicant: Ercan Adem ,  Nicholas H. Tripsas

Inventor： Ercan Adem ,  Nicholas H. Tripsas

IPC: H01L21/4763

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/76886

Abstract: Methods are described for eliminating void formation during the fabrication of and/or operation of memory cells/devices. According to one aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, formation of a diffusion barrier layer, deposition of a metal into the opening, preamorphization of the metal using preamorphization implants, and formation of a conductivity facilitating layer. According to another aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, formation of a diffusion barrier layer, deposition of a metal into the opening, preamorphization of the metal using a contact with a plasma, and formation of a conductivity facilitating layer.

Abstract translation: 描述了在存储器单元/器件的制造和/或操作期间消除空隙形成的方法。 根据本公开的一个方面，消除空隙的方法包括在半导体结构上形成开口，形成扩散阻挡层，将金属沉积到开口中，使用预变形植入物预先形成金属，以及形成 导电促进层。 根据本公开的另一方面，消除空隙的方法包括在半导体结构上形成开口，形成扩散阻挡层，将金属沉积到开口中，使用与等离子体接触进行金属预变质， 并形成导电促进层。

公开(公告)号：US07115498B1

公开(公告)日：2006-10-03

申请号：US10803852

申请日：2004-03-18

Applicant: Ercan Adem

Inventor： Ercan Adem

IPC: H01L21/4763

CPC classification number: H01L21/76843 ,  H01L21/76859 ,  H01L21/76871 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating an integrated circuit can include forming a barrier layer along lateral side walls and a bottom of a via aperture, forming a seed layer proximate and conformal to the barrier layer, and ion implanting elements into the seed layer. The via aperture is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer.

Abstract translation: 制造集成电路的方法可以包括沿着横向侧壁和通孔孔的底部形成阻挡层，形成接近势垒层并与形状保护层接合的种子层，以及离子注入元件到种子层中。 通孔被配置为接收电连接第一导电层和第二导电层的通孔材料。

公开(公告)号：US06770559B1

公开(公告)日：2004-08-03

申请号：US10282558

申请日：2002-10-29

Applicant: Ercan Adem ,  Fei Wang ,  Joffre F. Bernard

Inventor： Ercan Adem ,  Fei Wang ,  Joffre F. Bernard

IPC: H01L214763

CPC classification number: H01L21/76843 ,  H01L21/76859 ,  H01L21/76873 ,  H01L21/76874

Abstract: A conductive element of an integrated circuit wiring network is formed by a plating process. A seed layer for the conductive material is grown on the sidewalls and bottom surface of a trench using a low energy ion implantation process. The implantation is performed at an angle to the substrate to achieve coverage of the trench sidewalls. The resulting seed layer avoids constricting or closing the opening of the trench and has an approximately uniform thickness.

Abstract translation: 集成电路布线网络的导电元件通过电镀工艺形成。 使用低能离子注入工艺在沟槽的侧壁和底表面上生长用于导电材料的晶种层。 以与衬底成一定角度进行注入以实现沟槽侧壁的覆盖。 所得种子层避免收缩或关闭沟槽的开口并具有大致均匀的厚度。

公开(公告)号：US06208030B1

公开(公告)日：2001-03-27

申请号：US09179410

申请日：1998-10-27

Applicant: Ting Y. Tsui ,  Ercan Adem

Inventor： Ting Y. Tsui ,  Ercan Adem

IPC: H01L2348

CPC classification number: H01L23/5329 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.

Abstract translation: 通过处理电介质层以减小其介电常数，形成具有降低的电阻 - 电容时间常数的半导体器件。 实施例包括将沉积的介电层暴露于离子辐射，如同氦离子注入一样在层内形成空隙，由此降低其介电常数。