Wireless Receiver for removing direct current offset component
    11.
    发明申请
    Wireless Receiver for removing direct current offset component 有权
    用于去除直流偏移分量的无线接收器

    公开(公告)号:US20070280379A1

    公开(公告)日:2007-12-06

    申请号:US11443199

    申请日:2006-05-30

    IPC分类号: H04L27/22

    CPC分类号: H04L25/06 H03D7/00

    摘要: A wireless receiver includes a hardware (HW) block, a converter block and a digital signal processor (DSP). The HW block receives a wireless signal having a first DC Offset Component (DCOC), removes a portion of the first DCOC to produce a residual DCOC centered at DC, and generates parameters that estimate the residual DCOC. The converter block is coupled to the HW block and receives the residual DCOC centered at DC and converts it to a residual DCOC centered at IF. The DSP is coupled to the HW block and the converter block and receives the residual DCOC centered at IF from the converter block and the parameters from the HW block, and uses the parameters to eliminate the residual DCOC, and generate a baseband signal that is substantially free of the first DCOC and the residual DCOC.

    摘要翻译: 无线接收机包括硬件(HW)块,转换器块和数字信号处理器(DSP)。 HW块接收具有第一DC偏移分量(DCOC)的无线信号,去除第一DCOC的一部分以产生以DC为中心的残余DCOC,并产生估计残余DCOC的参数。 转换器块耦合到HW块并接收以DC为中心的残余DCOC,并将其转换为以IF为中心的残留DCOC。 DSP耦合到HW块和转换器模块,并从转换器模块接收以IF为中心的残留DCOC和来自HW模块的参数,并使用参数来消除残余DCOC,并生成基本信号 没有第一个DCOC和剩余的DCOC。

    Wireless communication device, integrated circuit and method of timing synchronisation
    12.
    发明授权
    Wireless communication device, integrated circuit and method of timing synchronisation 有权
    无线通信设备,集成电路和定时同步方法

    公开(公告)号:US08379627B2

    公开(公告)日:2013-02-19

    申请号:US12521862

    申请日:2007-01-02

    IPC分类号: H04J3/06 H04L12/28 H04L12/56

    CPC分类号: H04L7/04 H04J3/0685

    摘要: A wireless communication device comprises a first sub-system arranged to pass data to a second sub-system comprising timing synchronization logic operably coupled to a counter, such that data is sampled by the timing synchronization logic when passed to the second sub-system from the first sub-system wherein the wireless communication device is characterized in that the timing synchronization logic is arranged to determine a position of a first data frame and in response thereto initiate a counting process of the counter and determine a position of a second data frame and in response thereto determine a count value from the counting process of the counter and in response to the count value determine whether to initiate a timing advance or timing retard operation on the data being passed to the second sub-system. In this manner, the inventive concept provides the wireless communication device with a mechanism to achieve timing synchronization. In particular, the inventive concept may allow a radio frequency integrated circuit to implement timing synchronization by advancing or retarding an ‘actual’ signal sent from digital baseband circuits in a 3G DigRF wireless communication device.

    摘要翻译: 无线通信设备包括第一子系统,其被布置为将数据传递到第二子系统,该第二子系统包括可操作地耦合到计数器的定时同步逻辑,使得当数据被从第二子系统传送到第二子系统时由定时同步逻辑采样 第一子系统,其中所述无线通信装置的特征在于,所述定时同步逻辑被布置成确定第一数据帧的位置,并且响应于所述定时同步逻辑启动所述计数器的计数处理并且确定第二数据帧的位置 响应于此从计数器的计数处理确定计数值,并且响应于计数值确定是否对正被传递到第二子系统的数据启动定时提前或定时延迟操作。 以这种方式,本发明的概念为无线通信设备提供了实现定时同步的机制。 具体地,本发明的概念可以允许射频集成电路通过推进或延迟在3G DigRF无线通信设备中从数字基带电路发送的实际信号来实现定时同步。

    Methods and systems for combining timing signals for transmission over a serial interface
    13.
    发明授权
    Methods and systems for combining timing signals for transmission over a serial interface 有权
    用于组合定时信号以在串行接口上​​传输的方法和系统

    公开(公告)号:US08170166B2

    公开(公告)日:2012-05-01

    申请号:US12392841

    申请日:2009-02-25

    IPC分类号: H04L7/00

    CPC分类号: H04J3/0685 H04B1/40

    摘要: Apparatus, systems, and methods are provided for transmitting messages over a serial interface. A method comprises receiving a first signal at a first time and receiving a second signal at a second time, the second time being after the first time. If a difference between the second time and the first time is less than a threshold time period, the method comprises generating a first message that is representative of the first signal and the second signal and transmitting the first message over the serial interface. In accordance with one embodiment, the threshold time period is equal to one half of an interface acquisition delay time period associated with the serial interface.

    摘要翻译: 提供了用于通过串行接口发送消息的装置,系统和方法。 一种方法包括在第一时间接收第一信号并在第二时间接收第二信号,第二时间是在第一次之后。 如果第二时间和第一时间之间的差小于阈值时间段,则该方法包括生成表示第一信号和第二信号的第一消息,并通过串行接口发送第一消息。 根据一个实施例,阈值时间周期等于与串行接口相关联的接口获取延迟时间周期的一半。

    Wireless communication unit and power control system thereof
    14.
    发明授权
    Wireless communication unit and power control system thereof 有权
    无线通信单元及其功率控制系统

    公开(公告)号:US07991367B2

    公开(公告)日:2011-08-02

    申请号:US11722293

    申请日:2004-12-23

    IPC分类号: H04B1/04

    CPC分类号: H04W52/52 H03G3/3047

    摘要: A wireless communication unit comprises a transmitter having an analogue feedback power control loop having a power control function arranged to set an output power level of the transmitter. The power control function comprises a predictor sub-system arranged to reduce sensitivity to loop latency of the analogue feedback power control loop. The use of a predictor sub-system provides reduced sensitivity to loop latency, gain variations and delay.

    摘要翻译: 无线通信单元包括具有模拟反馈功率控制环路的发射机,该模拟反馈功率控制环路具有布置成设置发射机的输出功率电平的功率控制功能。 功率控制功能包括预测器子系统,其被布置为降低模拟反馈功率控制回路的环路延迟的灵敏度。 使用预测器子系统可以降低环路延迟,增益变化和延迟的灵敏度。

    Wireless receiver for removing direct current offset component
    15.
    发明授权
    Wireless receiver for removing direct current offset component 有权
    用于去除直流偏移分量的无线接收器

    公开(公告)号:US07593485B2

    公开(公告)日:2009-09-22

    申请号:US11443199

    申请日:2006-05-30

    IPC分类号: H04L25/06

    CPC分类号: H04L25/06 H03D7/00

    摘要: A wireless receiver includes a hardware (HW) block, a converter block and a digital signal processor (DSP). The HW block receives a wireless signal having a first DC Offset Component (DCOC), removes a portion of the first DCOC to produce a residual DCOC centered at DC, and generates parameters that estimate the residual DCOC. The converter block is coupled to the HW block and receives the residual DCOC centered at DC and converts it to a residual DCOC centered at IF. The DSP is coupled to the HW block and the converter block and receives the residual DCOC centered at IF from the converter block and the parameters from the HW block, and uses the parameters to eliminate the residual DCOC, and generate a baseband signal that is substantially free of the first DCOC and the residual DCOC.

    摘要翻译: 无线接收机包括硬件(HW)块,转换器块和数字信号处理器(DSP)。 HW块接收具有第一DC偏移分量(DCOC)的无线信号,去除第一DCOC的一部分以产生以DC为中心的残余DCOC,并产生估计残余DCOC的参数。 转换器块耦合到HW块并接收以DC为中心的残余DCOC,并将其转换为以IF为中心的残留DCOC。 DSP耦合到HW块和转换器模块,并从转换器模块接收以IF为中心的残留DCOC和来自HW模块的参数,并使用参数来消除残余DCOC,并生成基本信号 没有第一个DCOC和剩余的DCOC。

    Circuit and method of encoding and decoding digital data transmitted
along optical fibers
    18.
    发明授权
    Circuit and method of encoding and decoding digital data transmitted along optical fibers 失效
    对沿光纤传输的数字数据进行编码和解码的电路和方法

    公开(公告)号:US5673130A

    公开(公告)日:1997-09-30

    申请号:US582841

    申请日:1996-01-02

    摘要: A data transmitter (12) transmits parallel data as light pulses over multiple optical channels (14). A data receiver (16) converts the light pulses back to a voltage level and compares the voltage level to a reference capacitor voltage (42). The capacitor voltage should maintain a mid-range value for proper noise margin in detecting logic ones and logic zeroes. Any long series of consecutive logic ones or zeroes causes the capacitor voltage to charge or discharge toward the same level as the data voltage, which causes data errors. To prevent the data errors, the data is encoded (18) by inverting certain bits to break up the long series of consecutive logic states. The encoding information is transmitted as a transmitted clock to the data receiver over another fiber optic channel. The decoding information is retrieved (20) so that the encoded data can be converted back to proper logic states.

    摘要翻译: 数据发送器(12)将并行数据作为光脉冲发送在多个光通道(14)上。 数据接收器(16)将光脉冲转换回电压电平,并将电压电平与参考电容器电压(42)进行比较。 在检测逻辑和逻辑零时,电容电压应保持适当的噪声容限的中档值。 任何长串连续的逻辑或零都会使电容器电压与数据电压相同的电平进行充放电,从而导致数据错误。 为了防止数据错误,通过反转某些位来对数据进行编码(18)以分解长序列的连续逻辑状态。 编码信息作为发送时钟通过另一个光纤信道被发送到数据接收器。 检索解码信息(20),使得编码数据可被转换回适当的逻辑状态。

    Optoelectric interconnect and method for interconnecting an optical
fiber with an optoelectric device
    19.
    发明授权
    Optoelectric interconnect and method for interconnecting an optical fiber with an optoelectric device 失效
    用于将光纤与光电器件互连的光电互连和方法

    公开(公告)号:US5657409A

    公开(公告)日:1997-08-12

    申请号:US623244

    申请日:1996-03-28

    IPC分类号: G02B6/42 H01L27/15 G02B6/36

    摘要: An optoelectric interconnect (70) includes an optical fiber (17) coupled to a ferrule (11) and an optoelectric board (20). Metal layer (14) is disposed over a surface (12) of the ferrule (11). An optoelectric device (61) is coupled to the optoelectric board (20) using tape automated bonding tapes (47, 51). The optoelectric board (20) and the ferrule (11) are positioned adjacent each-other so that optical radiation is transmitted from the optoelectric device (61) to the optical fiber (17). The position of the optoelectric device (61) is adjusted to achieve an optimum position which is characterized by a maximum optical radiation transmitted to the optical fiber(17). Upon achieving the optimum position, two bonding strips (54, 56) are fused with the metal layer (14) on the surface (12) of the ferrule (11).

    摘要翻译: 光电互连(70)包括耦合到套圈(11)和光电板(20)的光纤(17)。 金属层(14)设置在套圈(11)的表面(12)上方。 光电装置(61)使用胶带自动粘结胶带(47,51)与光电板(20)连接。 光电板(20)和套圈(11)彼此相邻地定位,使得光辐射从光电装置(61)传输到光纤(17)。 调整光电器件(61)的位置以实现最佳位置,其特征在于传输到光纤(17)的最大光辐射。 在达到最佳位置时,两个接合条(54,56)与金属层(14)熔合在套圈(11)的表面(12)上。

    POWER CONTROL SYSTEM FOR A WIRELESS COMMUNICATION UNIT
    20.
    发明申请
    POWER CONTROL SYSTEM FOR A WIRELESS COMMUNICATION UNIT 有权
    无线通信单元功率控制系统

    公开(公告)号:US20100009642A1

    公开(公告)日:2010-01-14

    申请号:US11722296

    申请日:2004-12-23

    IPC分类号: H04B1/04

    摘要: A wireless communication unit comprises a transmitter having an analogue feedback power control loop with an input and a power amplifier having a power amplifier output, where the analogue feedback power control loop is arranged to feedback a signal to the input to set an output power level of the transmitter. The wireless communication unit further comprises an outer digital loop operably coupled from the power amplifier output to the transmitter.In this manner, the inner analogue loop is used to linearise a response obtained from the power amplifier and an outer digital loop wherein the outer digital loop controls the inner analogue loop with regard to saturation detection and correction as well as facilitating multi-mode operation of the wireless communication unit.

    摘要翻译: 无线通信单元包括具有模拟反馈功率控制环路的发射机,具有输入端和功率放大器,功率放大器具有功率放大器输出,其中模拟反馈功率控制环路被布置成将信号反馈到输入端以设置输出功率电平 发射机。 无线通信单元还包括可操作地从功率放大器输出耦合到发射器的外部数字环路。 以这种方式,内部模拟环路用于线性化从功率放大器和外部数字环路获得的响应,其中外部数字环路相对于饱和度检测和校正控制内部模拟环路以及促进多模式操作 无线通信单元。