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80 条记录 (耗时 0.033 秒)

    Network processor probing and port mirroring
    12.
    发明授权
    Network processor probing and port mirroring 失效
    网络处理器探测和端口镜像

    公开(公告)号：US06449576B1

    公开(公告)日：2002-09-10

    申请号：US09538247

    申请日：2000-03-29

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken ,  Chad Everett Winemiller

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken ,  Chad Everett Winemiller

    IPC分类号： G01R2728

    CPC分类号： H04L43/50 ,  G01R31/31926

    摘要： A method and system for systematically accessing and monitoring operating parameter signals within an IC device. A probe configuration logic selects a subset of signals from among a set of available signals within a physical or logical subdivision of the IC device. Signal access logic selectively provides physical or logical access from the selected subset of signals within the physical or logical subdivision of the IC device to a probe sensor, such that IC device operations may be flexibly and comprehensively monitored. A local mode selector provides remote access to the selected subset of signals at an input/output (I/O) data interface. Data packaging logic in communication with the probe sensor permits port mirroring of the I/O data interface.

    摘要翻译： 一种用于系统地访问和监视IC设备内的操作参数信号的方法和系统。 探针配置逻辑从IC器件的物理或逻辑细分内的一组可用信号中选择一个信号子集。 信号访问逻辑选择性地从IC器件的物理或逻辑细分中的选定的信号子集提供到探针传感器的物理或逻辑访问，使得可以灵活和全面地监视IC器件操作。 本地模式选择器可在输入/输出（I / O）数据接口上远程访问选定的信号子集。 与探头传感器通信的数据封装逻辑允许端口镜像I / O数据接口。

    Network processor for multiprotocol data flows
    17.
    发明授权
    Network processor for multiprotocol data flows 有权
    用于多协议数据流的网络处理器

    公开(公告)号：US06671280B1

    公开(公告)日：2003-12-30

    申请号：US09535794

    申请日：2000-03-29

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： H04L1256

    CPC分类号： H04L49/30 ,  H04L45/502 ,  H04L49/201 ,  H04L49/251 ,  H04L49/3009 ,  H04L49/602 ,  H04L49/606 ,  H04L2012/5618 ,  H04L2012/5665

    摘要： A method for integrating Asynchronous Transfer Mode (ATM) and frame-based traffic flows within a telecommunications network is disclosed. The telecommunications network includes a network processor having upside processing means for delivering an incoming flow from the telecommunications network to a switch and downside processing means for delivering outgoing network traffic from the switch to the telecommunications network. The incoming flow is initially received at the upside processing means as a frame-based flow. The incoming flow may be characterized as belonging to a group having frame-based flows and ATM flows. In response to the receipt of the incoming flow, the incoming flow is determined if it is destined for a legacy, ATM-only device. The incoming flow is then processed according to the determined routing requirements and the incoming flow characterization before delivering the incoming flow to the switch.

    摘要翻译： 公开了一种在电信网络内集成异步传输模式（ATM）和基于帧的业务流的方法。 电信网络包括具有上行处理装置的网络处理器，用于将来自电信网络的输入流传送到交换机，以及下行处理装置，用于将来自交换机的输出网络业务传送到电信网络。 最初在上行处理装置处接收输入流作为基于帧的流。 输入流可以被表征为属于具有基于帧的流和ATM流的组。 响应于接收到的流入，确定进入流是否发往传统的仅ATM设备。 然后根据确定的路由要求和输入流特性，将传入流量传送到交换机之前处理进入流。

    Queue manager for a buffer
    18.
    发明授权
    Queue manager for a buffer 失效
    队列管理器为缓冲区

    公开(公告)号：US06557053B1

    公开(公告)日：2003-04-29

    申请号：US09477179

    申请日：2000-01-04

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Michael Raymond Trombley ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Michael Raymond Trombley ,  Fabrice Jean Verplanken

    IPC分类号： G06F1314

    CPC分类号： G06F13/1673

    摘要： A bandwidth conserving queue manager for a FIFO buffer is provided, preferably on an ASIC chip and preferably including separate DRAM storage that maintains a FIFO queue which can extend beyond the data storage space of the FIFO buffer to provide additional data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multiple queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffer storage space in the FIFO buffers is exceeded, data are written to and read from the additional data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a way that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.

    摘要翻译： 提供了用于FIFO缓冲器的带宽保存队列管理器，优选地在ASIC芯片上，并且优选地包括分离的DRAM存储器，其维持FIFO队列，其可以超出FIFO缓冲器的数据存储空间，以根据需要提供附加的数据存储空间。 在ASIC芯片上使用FIFO缓冲器来存储和检索多个队列条目。 只要队列的总大小不超过缓冲区中可用的存储空间，则不需要额外的数据存储。 然而，当超过FIFO缓冲器中的一些预定量的缓冲存储空间时，数据被写入附加数据存储器并从其中读出，并且优选地是具有用于保持数据存储设备的峰值性能的最佳尺寸的数据包，以及哪个 被写入数据存储设备，使得它们以先入先出（FIFO）地址序列排队。 优选地，以突发模式将数据写入DRAM并从DRAM读取。

    Method and system for network processor scheduling outputs using queueing
    20.
    发明授权
    Method and system for network processor scheduling outputs using queueing 失效
    使用排队的网络处理器调度输出的方法和系统

    公开(公告)号：US06952424B1

    公开(公告)日：2005-10-04

    申请号：US09548912

    申请日：2000-04-13

    申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

    IPC分类号： H04L12/28 ,  H04L12/56 ,  H04L29/06

    CPC分类号： H04L49/90

    摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a weighted fair queueing system where the position of the next service in a best efforts system for using bandwidth which is not used by committed bandwidth is determined based on the length of the frame and the weight of the particular flow. A “back pressure” system keeps a flow from being selected if its output cannot accept an additional frame because the current level of that port queue exceeds a threshold.

    摘要翻译： 一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。 本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。 优选实施例中的优先级包括低延迟服务，最小带宽，加权公平排队以及用于在较长时间内防止用户继续超过其服务水平的系统。 本发明包括一个加权公平排队系统，其中基于帧的长度和特定流的权重确定用于使用未被承诺带宽使用的带宽的最佳努力系统中的下一个服务的位置。 如果该端口队列的当前级别超过阈值，则“背压”系统的输出不能接受额外的帧，从而保持流量的选择。