公开(公告)号：US08659337B2

公开(公告)日：2014-02-25

申请号：US13188364

申请日：2011-07-21

申请人： Ilyas Elkin ,  William James Dally ,  Jonah M. Alben

发明人： Ilyas Elkin ,  William James Dally ,  Jonah M. Alben

IPC分类号： H03K3/356

CPC分类号： H03K3/356 ,  H03K3/356026 ,  H03K3/356052 ,  H03K3/356147 ,  H03K3/356191

摘要： One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.

摘要翻译： 本发明的一个实施例提出了一种使用向时钟信号呈现低负载的锁存电路来捕获和保持输入信号电平的技术。 时钟仅耦合到桥接晶体管和一对时钟激活的下拉或上拉晶体管。 当存储子电路未使能时，输入信号的电平被传播到输出信号。 存储子电路由桥接晶体管使能，传播子电路由一对时钟激活晶体管激活和去激活。

公开(公告)号：US08604857B2

公开(公告)日：2013-12-10

申请号：US13294025

申请日：2011-11-10

申请人： William James Dally

发明人： William James Dally

IPC分类号： H03H11/26

CPC分类号： H03H11/265

摘要： One embodiment of the present invention sets forth a technique for reducing jitter caused by changes in a power supply for a clock generated by a ring oscillator of inverter devices. An inverter sub-circuit is coupled in parallel with a current-starved inverter sub-circuit to produce an inverter circuit that is insensitive to changes in the power supply voltage. When the ring oscillator is used as the voltage controlled oscillator of a phase locked loop, the delay of the inverters may be controlled by varying a bias current for each inverter in response to changes in the power supply voltage to reduce any jitter in a clock output produced by the changes in the power supply voltage. When the transistor devices are sized appropriately and the bias current is adjusted, the sensitivity of the inverter circuit to changes in the power supply voltage may be reduced.

摘要翻译： 本发明的一个实施例提出了一种用于减少由逆变器装置的环形振荡器产生的时钟的电源的变化引起的抖动的技术。 逆变器子电路与电流欠压逆变器子电路并联耦合，以产生对电源电压变化不敏感的逆变器电路。 当环形振荡器用作锁相环的压控振荡器时，可以通过响应于电源电压的变化改变每个逆变器的偏置电流来控制反相器的延迟，以减少时钟输出中的任何抖动 由电源电压的变化产生。 当晶体管器件的尺寸适当并且调节偏置电流时，可以减小逆变器电路对电源电压变化的灵敏度。

公开(公告)号：US08788761B2

公开(公告)日：2014-07-22

申请号：US13243948

申请日：2011-09-23

申请人： William James Dally

发明人： William James Dally

IPC分类号： G06F12/08

CPC分类号： G06F12/0817 ,  G06F12/0842

摘要： One embodiment of the present invention sets forth am extension to a cache coherence protocol with two explicit control states, P (private), and R (read-only), that provide explicit program control of cache lines for which the program logic can guarantee correct behavior. In the private state, only the owner of a cache line can access the cache line for read or write operations. In the read-only state, only read operations can be performed on the cache line, thereby disallowing write operations to be performed.

摘要翻译： 本发明的一个实施例阐述了对具有两个显式控制状态P（私有）和R（只读））的高速缓存一致性协议的扩展，其提供对程序逻辑可以保证正确的高速缓存行的显式程序控制 行为。 在私有状态下，只有高速缓存行的所有者可以访问高速缓存行进行读取或写入操作。 在只读状态下，只能对高速缓存线执行读操作，从而不允许执行写操作。

公开(公告)号：US08689159B1

公开(公告)日：2014-04-01

申请号：US13612629

申请日：2012-09-12

申请人： Robert Palmer ,  John W. Poulton ,  Thomas Hastings Greer, III ,  William James Dally

发明人： Robert Palmer ,  John W. Poulton ,  Thomas Hastings Greer, III ,  William James Dally

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： One embodiment sets forth a technique for on-chip satisfying timing requirements of on-chip source-synchronous, CMOS-repeater-based interconnect. Each channel of the on-chip interconnect may include one or more redundant wires. Calibration logic is configured to apply transition patterns to wires comprising each channel and calibration patterns that are generated in response to the transition patterns are captured. Based on the calibration patterns, wires that best satisfy the timing requirements of the on-chip interconnect are selected for use to transmit data. The calibration logic also trims the delays of the clock and selected data wires based on captured calibration patterns to improve the timing margin of the on-chip interconnect. Improving the timing margin of the on-chip interconnect improves chip yields.

摘要翻译： 一个实施例提出了片上源同步，基于CMOS中继器的互连的片上满足定时要求的技术。 片上互连的每个通道可以包括一个或多个冗余电线。 校准逻辑被配置为将转换模式应用于包括每个通道的线和响应于捕获转换模式而生成的校准图案。 基于校准模式，选择最能满足片上互连的时序要求的导线用于传输数据。 校准逻辑还基于捕获的校准模式修整时钟和所选数据线的延迟，以提高片上互连的时序裕度。 提高片上互连的时序裕度提高了芯片产量。

公开(公告)号：US08941430B2

公开(公告)日：2015-01-27

申请号：US13612614

申请日：2012-09-12

申请人： Robert Palmer ,  John W. Poulton ,  Thomas Hastings Greer, III ,  William James Dally

发明人： Robert Palmer ,  John W. Poulton ,  Thomas Hastings Greer, III ,  William James Dally

IPC分类号： H03H11/26

CPC分类号： H03K5/131 ,  H01L2924/0002 ,  H03K5/133 ,  H01L2924/00

摘要： One embodiment sets forth a timing calibration technique for on-chip source-synchronous, complementary metal-oxide-semiconductor (CMOS) repeater-based interconnect. Two transition patterns may be applied to calibrate the delay of an on-chip data or clock wire. Calibration logic is configured to apply the transition patterns and then trim the delays of the clock and data wires based on captured calibration patterns. The trimming adjusts the delay of the clock and data wires using a configurable delay circuit. Timing errors may be caused by crosstalk, power-supply-induced jitter (PSIJ), or wire delay variation due to transistor and wire metallization mismatch. Chip yields may be improved by reducing the occurrence of timing errors due to mismatched delays between different wires of an on-chip interconnect.

摘要翻译： 一个实施例提出了用于片上源同步，互补金属氧化物半导体（CMOS）基于中继器的互连的定时校准技术。 可以应用两个转换模式来校准片上数据或时钟线的延迟。 校准逻辑被配置为应用转换模式，然后基于捕获的校准模式修剪时钟和数据线的延迟。 微调使用可配置的延迟电路来调整时钟和数据线的延迟。 定时误差可能由串扰，电源引起的抖动（PSIJ）或由于晶体管和导线金属化不匹配引起的导线延迟变化引起。 可以通过减少由于片上互连的不同导线之间的不匹配延迟引起的定时误差的出现来提高芯片产量。

公开(公告)号：US20140077857A1

公开(公告)日：2014-03-20

申请号：US13619765

申请日：2012-09-14

申请人： John W. POULTON ,  Robert Palmer ,  William James Dally

发明人： John W. POULTON ,  Robert Palmer ,  William James Dally

IPC分类号： H03H11/26

CPC分类号： H03K5/133

摘要： One embodiment sets forth a technique for delaying signals by varying amounts. A configurable delay circuit includes fixed and tri-state inverters. Pullup and pulldown transistors within one or more tri-state inverters may be activated to reduce the delay introduced by fixed inverters. The pullup and pulldown transistors within one or more tri-state inverters may be separately activated to independently adjust the rising delay and the falling delay incurred by the input signal.

摘要翻译： 一个实施例提出了用于通过变化的量来延迟信号的技术。 可配置的延迟电路包括固定和三态逆变器。 一个或多个三态反相器中的上拉和下拉晶体管可以被激活以减少由固定逆变器引入的延迟。 一个或多个三态反相器中的上拉和下拉晶体管可以单独激活，以独立地调节由输入信号引起的上升延迟和下降延迟。

公开(公告)号：US20120079201A1

公开(公告)日：2012-03-29

申请号：US13243948

申请日：2011-09-23

申请人： William James Dally

发明人： William James Dally

IPC分类号： G06F12/08

CPC分类号： G06F12/0817 ,  G06F12/0842

摘要： One embodiment of the present invention sets forth am extension to a cache coherence protocol with two explicit control states, P (private), and R (read-only), that provide explicit program control of cache lines for which the program logic can guarantee correct behavior. In the private state, only the owner of a cache line can access the cache line for read or write operations. In the read-only state, only read operations can be performed on the cache line, thereby disallowing write operations to be performed.

摘要翻译： 本发明的一个实施例阐述了对具有两个显式控制状态P（私有）和R（只读））的高速缓存一致性协议的扩展，其提供对程序逻辑可以保证正确的高速缓存行的显式程序控制 行为。 在私有状态下，只有高速缓存行的所有者可以访问高速缓存行进行读取或写入操作。 在只读状态下，只能对高速缓存线执行读操作，从而不允许执行写操作。