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公开(公告)号：US12246536B2
公开(公告)日：2025-03-11
申请号：US17537804
申请日：2021-11-30
Applicant: CANON KABUSHIKI KAISHA
Inventor： Yasuo Fujii , Yasuhiro Soeda , Yosuke Miura
IPC: B41J2/14
Abstract: Provided is a technique that enables voltages to be applied, with high precision, to an electrode layer for inhibition and removal of koge while suppressing increase in the size a substrate. A liquid ejection head substrate includes: electrothermal conversion elements that apply heat to a liquid; an upper electrode part in which a plurality of upper electrodes that protect the electrothermal conversion elements are formed at positions where the upper electrodes come into contact with the liquid; a counter electrode part which is provided to correspond to the upper electrode part and in which a plurality of counter electrodes are formed to be electrically connectable to the upper electrodes via the liquid; and a generation unit that generates a voltage to be applied to at least one of the upper electrode part and the counter electrode part.
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公开(公告)号：US20240379179A1
公开(公告)日：2024-11-14
申请号：US18779769
申请日：2024-07-22
Applicant: CANON KABUSHIKI KAISHA
Inventor： Suguru Taniguchi , Toshio Negishi , Yasuhiro Soeda
Abstract: A switch is configured to switch connection between a second terminal to which a data signal is input and a memory control signal of a memory element in accordance with a switching signal included in a data signal. In write to a memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for the write to the memory element is input via the second terminal.
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公开(公告)号：US12046309B2
公开(公告)日：2024-07-23
申请号：US17691291
申请日：2022-03-10
Applicant: CANON KABUSHIKI KAISHA
Inventor： Suguru Taniguchi , Toshio Negishi , Yasuhiro Soeda
CPC classification number: G11C17/16 , B41J2/04541 , B41J2/04543 , B41J2/0458 , B41J2202/17
Abstract: A switch is configured to switch connection between a second terminal to which a data signal is input and a memory control signal of a memory element in accordance with a switching signal included in a data signal. In write to a memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for the write to the memory element is input via the second terminal.
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Patent Agency Ranking
公开(公告)号：US20230074434A1
公开(公告)日：2023-03-09
申请号：US17901033
申请日：2022-09-01
Applicant: CANON KABUSHIKI KAISHA
Inventor： Yosuke Miura , Yasuo Fujii , Yasuhiro Soeda
IPC: B41J2/14
Abstract: According to the present invention, it is possible to provide an element substrate and a print head with which a decrease in yield and an increase in cost in a manufacturing process can be suppressed. For that purpose, a VH wiring line and a GNDH wiring line are provided in parallel in the same layer.
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公开(公告)号：US10126190B2
公开(公告)日：2018-11-13
申请号：US15310421
申请日：2015-04-24
Applicant: CANON KABUSHIKI KAISHA
Inventor： Yasuhiro Soeda , Yasuhiro Shimada
Abstract: A capacitive force sensor 101 of the present invention includes a plurality of cells each including a lower electrode 104, a movable member that includes an upper electrode 107 and has flexibility, and a support 105b arranged to movably support the movable member and to form a gap 106 between the upper and the lower electrodes. The plural cells are grouped into elements each including one or more of the cells, and the one or more cells in a same element are electrically connected to each other.
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公开(公告)号：US20130321039A1
公开(公告)日：2013-12-05
申请号：US13897018
申请日：2013-05-17
Applicant: CANON KABUSHIKI KAISHA
Inventor： Yasuhiro Soeda
IPC: H03K3/01
CPC classification number: H03K3/01 , B06B1/0207 , B06B1/0292 , B06B2201/51 , B06B2201/76
Abstract: A measuring device comprises a plurality of variable capacitors as sensor elements. The plurality of variable capacitors are provided with a drive circuit for each pair. The first electrodes of the two variable capacitors in each pair are electrically connected to each other. The drive circuit for each pair includes a bias supply for applying two AC bias voltages relatively 90° out of phase to the second electrodes respectively of the two variable capacitors to produce an output signal at the first electrodes connected to each other, a multiplier for multiplying the output signal by two AC signals relatively 90° out of phase to produce two multiplication signals, and an integrator for integrating the two multiplication signals for each cycle of the corresponding AC bias voltages to acquire two integration signals for the two variable capacitors.
Abstract translation: 测量装置包括多个可变电容器作为传感器元件。 多个可变电容器为每对设置有驱动电路。 每对中的两个可变电容器的第一电极彼此电连接。 每对的驱动电路包括偏置电源，用于将相对于相对于相位相差90°的两个AC偏置电压分别施加到两个可变电容器的第二电极，以在彼此连接的第一电极处产生输出信号，乘法器 两个交流信号的输出信号相差90°以产生两个相乘信号，以及积分器，用于对相应AC偏置电压的每个周期对两个乘法信号进行积分，以获得两个可变电容器的两个积分信号。
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公开(公告)号：US11837301B2
公开(公告)日：2023-12-05
申请号：US17685479
申请日：2022-03-03
Applicant: CANON KABUSHIKI KAISHA
Inventor： Masashi Fukuda , Toshio Negishi , Yasuhiro Soeda
CPC classification number: G11C17/165 , G11C5/14 , G11C7/1096
Abstract: A substrate includes a plurality of memory units each including an anti-fuse element and a switching element configured to switch application of a predetermined voltage to the anti-fuse element, a wiring to which the plurality of memory units are connected, a first electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied, and a second electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied.
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公开(公告)号：US20220293201A1
公开(公告)日：2022-09-15
申请号：US17687482
申请日：2022-03-04
Applicant: CANON KABUSHIKI KAISHA
Inventor： Sadayoshi Sakuma , Toshio Negishi , Yasuhiro Soeda
IPC: G11C17/16 , G11C17/18 , H01L27/112 , B41J2/045
Abstract: A device, comprising a plurality of units arrayed in a predetermined direction, a first terminal configured to supply a voltage to the plurality of units, and a second terminal configured to supply a voltage to the plurality of units, wherein the plurality of units include a first unit including a memory element arranged between the first terminal and the second terminal, and a first transistor configured to perform write to the memory element, and a second unit including a second transistor arranged between the first terminal and the second terminal in correspondence with the first transistor of the first unit.
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