公开(公告)号：US20170173953A1

公开(公告)日：2017-06-22

申请号：US15382079

申请日：2016-12-16

Applicant: CANON KABUSHIKI KAISHA

Inventor： Suguru Taniguchi ,  Koichi Omata ,  Hideo Tamura ,  Takaaki Yamaguchi ,  Kousuke Kubo ,  Ryoji Oohashi ,  Yuji Tamaru ,  Toshio Negishi ,  Yohei Osuki

IPC: B41J2/14

CPC classification number: B41J2/14145 ,  B41J2/1404 ,  B41J2/14072 ,  B41J2/14112 ,  B41J2/14129

Abstract: A recording-element substrate includes a substrate including a base member, a pair of electrodes, a heating element formed of a thermal resistor layer between the electrodes, a surface on which an electroconductive film coating the heating element has been formed, and an insulating film between the heating element and the electroconductive film and a flow-path-forming member including walls forming a liquid flow path toward the heating element while being disposed on the substrate's surface side. The substrate includes an electric connecting portion in contact with the electroconductive film to connect the electroconductive film with the base member. The shortest distance between the electric connecting portion and a portion where an angle formed by the walls is 120 degrees or smaller when viewed from a direction orthogonal to the surface is smaller than that between a boundary between the electrodes and the heating element and the portion.

公开(公告)号：US11845274B2

公开(公告)日：2023-12-19

申请号：US17569946

申请日：2022-01-06

Applicant: CANON KABUSHIKI KAISHA

Inventor： Toshio Negishi ,  Suguru Taniguchi ,  Kazunari Fujii

IPC: B41J2/14

CPC classification number: B41J2/14072 ,  B41J2/14024 ,  B41J2202/20

Abstract: A recording element substrate for a liquid ejection head is provided with a storage section including an antifuse element and a first resistor connected in parallel with the antifuse element, and a second resistor that is connected in parallel with the storage section and serves as a reference in rating information of the antifuse element, and a second switch connected to the second resistor.

公开(公告)号：US20220126576A1

公开(公告)日：2022-04-28

申请号：US17569946

申请日：2022-01-06

Applicant: CANON KABUSHIKI KAISHA

Inventor： Toshio Negishi ,  Suguru Taniguchi ,  Kazunari Fujii

IPC: B41J2/14

Abstract: A recording element substrate for a liquid ejection head is provided with a storage section including an antifuse element and a first resistor connected in parallel with the antifuse element, and a second resistor that is connected in parallel with the storage section and serves as a reference in rating information of the antifuse element, and a second switch connected to the second resistor.

公开(公告)号：US20200207089A1

公开(公告)日：2020-07-02

申请号：US16723955

申请日：2019-12-20

Applicant: CANON KABUSHIKI KAISHA

Inventor： Toshio Negishi ,  Suguru Taniguchi ,  Kazunari Fujii

IPC: B41J2/14

Abstract: A recording element substrate for a liquid ejection head is provided with a storage section including an antifuse element and a first resistor connected in parallel with the antifuse element, and a second resistor that is connected in parallel with the storage section and serves as a reference in rating information of the antifuse element, and a second switch connected to the second resistor.

公开(公告)号：US11247461B2

公开(公告)日：2022-02-15

申请号：US16723955

申请日：2019-12-20

Applicant: CANON KABUSHIKI KAISHA

Inventor： Toshio Negishi ,  Suguru Taniguchi ,  Kazunari Fujii

IPC: B41J2/14 ,  B41J2/16

Abstract: A recording element substrate for a liquid ejection head is provided with a storage section including an antifuse element and a first resistor connected in parallel with the antifuse element, and a second resistor that is connected in parallel with the storage section and serves as a reference in rating information of the antifuse element, and a second switch connected to the second resistor.

公开(公告)号：US10189249B2

公开(公告)日：2019-01-29

申请号：US15895949

申请日：2018-02-13

Applicant: CANON KABUSHIKI KAISHA

Inventor： Suguru Taniguchi ,  Toshio Negishi ,  Kazunari Fujii

IPC: B41J2/175 ,  B41J2/045

Abstract: A recording element substrate includes a recording module including a plurality of recording elements and first logic circuits corresponding to the plurality of recording elements, a memory module including a plurality of memory elements and second logic circuits corresponding to the plurality of memory elements, and a common line configured to connect a signal supply circuit to the plurality of first logic circuits and the plurality of second logic circuits in common. The recording elements are arranged along an extending direction in which the common line extends, and the memory modules are disposed between the common line and the recording elements.

公开(公告)号：US20180104954A1

公开(公告)日：2018-04-19

申请号：US15692105

申请日：2017-08-31

Applicant: CANON KABUSHIKI KAISHA

Inventor： Yohei Osuki ,  Koichi Omata ,  Hideo Tamura ,  Takaaki Yamaguchi ,  Kousuke Kubo ,  Ryoji Oohashi ,  Yuji Tamaru ,  Toshio Negishi ,  Suguru Taniguchi

IPC: B41J2/14

CPC classification number: B41J2/14072 ,  B41J2/14088 ,  B41J2/14129 ,  B41J2202/13

Abstract: A print element substrate, comprises: a heater layer; a wiring layer that is connected to the heater layer and is for causing the heater layer to generate heat; an insulating layer arranged on the wiring layer; an anti-cavitation layer arranged on the insulating layer that is for protecting the insulating layer; and a switch that has a control terminal that is pulled-down to a ground, and causes the anti-cavitation layer and the ground to have an electrical connection when the control terminal is in a high-level state.

公开(公告)号：US20170100930A1

公开(公告)日：2017-04-13

申请号：US15287379

申请日：2016-10-06

Applicant: CANON KABUSHIKI KAISHA

Inventor： Ryoji Oohashi ,  Koichi Omata ,  Hideo Tamura ,  Takaaki Yamaguchi ,  Kousuke Kubo ,  Suguru Taniguchi ,  Yuji Tamaru ,  Toshio Negishi ,  Yohei Osuki

IPC: B41J2/14

CPC classification number: B41J2/1433 ,  B41J2/14072 ,  B41J2/14088 ,  B41J2/14129 ,  B41J2/14201 ,  B41J2/1603 ,  B41J2/1631 ,  B41J2/1635 ,  B41J2/1642 ,  B41J2/1646 ,  B41J2002/14217

Abstract: An element substrate for a liquid ejecting head includes a substrate, an element forming layer on the substrate, and a discharge port forming member formed of an insulating member on the element forming layer. The element forming layer includes an energy generating element configured to provide energy to a liquid for ejection. The discharge port forming member includes a discharge port forming surface having discharge ports through which the liquid is ejected and an exterior side surface positioned between the discharge port forming surface and the element forming layer. The exterior side surface has a first edge facing the element forming layer. The element substrate further includes a conductive layer disposed between the first edge and the element forming layer and grounded.

公开(公告)号：US20220293199A1

公开(公告)日：2022-09-15

申请号：US17691291

申请日：2022-03-10

Applicant: CANON KABUSHIKI KAISHA

Inventor： Suguru Taniguchi ,  Toshio Negishi ,  Yasuhiro Soeda

IPC: G11C17/16 ,  B41J2/14 ,  B41J2/175

Abstract: A switch is configured to switch connection between a second terminal to which a data signal is input and a memory control signal of a memory element in accordance with a switching signal included in a data signal. In write to a memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for the write to the memory element is input via the second terminal.

公开(公告)号：US20180236762A1

公开(公告)日：2018-08-23

申请号：US15901619

申请日：2018-02-21

Applicant: CANON KABUSHIKI KAISHA

Inventor： Toshio Negishi ,  Suguru Taniguchi ,  Kazunari Fujii

IPC: B41J2/045 ,  H01L27/112 ,  H01L23/528

CPC classification number: B41J2/04541 ,  B41J2/04523 ,  B41J2/0455 ,  B41J2/0458 ,  B41J2/14072 ,  B41J2/17546 ,  B41J2202/13 ,  G11C17/14 ,  H01L27/11206

Abstract: A recording element substrate includes a signal supply circuit and a common line which connects the signal supply circuit to first logic circuit array for a recording element and a second logic circuit array for a memory element in common. Furthermore, the first and second logic circuit arrays extend along a direction in which the common line extends, the first logic circuit array is disposed on one side of the common line, the second logic circuit array is disposed on the other side of the common line, and the first and second logic circuit arrays are arranged so that at least a portion of the first logic circuit array and a portion of the second logic circuit array overlap with each other in a direction orthogonal to the extending direction.