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公开(公告)号：US11981129B2
公开(公告)日：2024-05-14
申请号：US17691281
申请日：2022-03-10
Applicant: CANON KABUSHIKI KAISHA
Inventor： Soichiro Nagamochi , Toshio Negishi , Yasuhiro Soeda
CPC classification number: B41J2/04541 , B41J2/04536 , B41J2/04586 , G11C17/16 , G11C17/18
Abstract: An element substrate comprises a plurality of stages of shift registers that inputs and holds a serial data signal; a latch circuit that latches the serial data held by the shift registers; a decoder circuit that inputs an output of the latch circuit and outputs a selection signal for selecting a block of the print elements or the memory elements; and a mask circuit that masks the output of the selection signal for selecting the block of the memory elements from the decoder circuit in accordance with an input bit data signal. The block of the print elements or the memory elements includes a plurality of print elements or memory elements in which one element is selected in each of the plurality of groups.
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公开(公告)号：US20220293200A1
公开(公告)日：2022-09-15
申请号：US17685479
申请日：2022-03-03
Applicant: CANON KABUSHIKI KAISHA
Inventor： Masashi Fukuda , Toshio Negishi , Yasuhiro Soeda
Abstract: A substrate includes a plurality of memory units each including an anti-fuse element and a switching element configured to switch application of a predetermined voltage to the anti-fuse element, a wiring to which the plurality of memory units are connected, a first electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied, and a second electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied.
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公开(公告)号：US08754490B2
公开(公告)日：2014-06-17
申请号：US13906672
申请日：2013-05-31
Applicant: Canon Kabushiki Kaisha
Inventor： Takahiro Ezaki , Chienliu Chang , Yasuhiro Soeda , Kenji Tamamori
IPC: H01L29/84 , H01L21/00 , B06B1/02 , H01L23/522 , H01L27/12 , H01L21/768
CPC classification number: H01L23/5226 , B06B1/0292 , B81B2201/0257 , H01L21/76898 , H01L27/1203 , H01L29/84 , H01L2924/0002 , H01L2924/00
Abstract: An element array comprises a plurality of elements having a first electrode and a second electrode with a gap therebetween; the first electrode is separated for each of the elements by grooves, an insulating connection substrate is bonded to the first electrode, and wirings are provided from the respective first electrodes through the connection substrate to the side opposite to the first electrodes.
Abstract translation: 元件阵列包括具有第一电极和第二电极的多个元件，其间具有间隙; 通过沟槽将每个元件分离第一电极，绝缘连接衬底接合到第一电极，并且通过连接衬底从相应的第一电极到与第一电极相对的一侧提供布线。
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公开(公告)号：US11975536B2
公开(公告)日：2024-05-07
申请号：US17670325
申请日：2022-02-11
Applicant: CANON KABUSHIKI KAISHA
Inventor： Toshio Negishi , Yasuhiro Soeda
CPC classification number: B41J2/04541 , G11C17/16 , G11C17/18 , B41J2/0458
Abstract: An element substrate including a liquid discharge element, comprising a memory element capable of storing individual information of the element substrate by a write, the memory element being configured to change an impedance value by the write, a plurality of current supply elements capable of supplying a current to the memory element, and a determination unit configured to determine presence/absence of the write based on a voltage generated in the memory element by the current selectively supplied from the plurality of current supply elements, wherein the plurality of current supply elements constitute a part of a current mirror circuit and each supply the current in an amount according to a size ratio to the memory element.
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公开(公告)号：US20170074734A1
公开(公告)日：2017-03-16
申请号：US15310421
申请日：2015-04-24
Applicant: CANON KABUSHIKI KAISHA
Inventor： Yasuhiro Soeda , Yasuhiro Shimada
CPC classification number: G01L5/228 , B06B1/0215 , B06B1/0292 , G01L1/144 , G01L1/146 , G01L1/148 , G01L9/0072 , G01L9/0073 , G01L9/0086 , G01N29/2406 , G05B2219/39107 , G05B2219/39508 , G05B2219/39527
Abstract: A capacitive force sensor 101 of the present invention includes a plurality of cells each including a lower electrode 104, a movable member that includes an upper electrode 107 and has flexibility, and a support 105b arranged to movably support the movable member and to form a gap 106 between the upper and the lower electrodes. The plural cells are grouped into elements each including one or more of the cells, and the one or more cells in a same element are electrically connected to each other.
Abstract translation: 本发明的电容式力传感器101包括多个单元，每个单元包括下电极104，包括上电极107并具有柔性的可移动构件，以及支撑件105b，其布置成可移动地支撑可移动构件并形成间隙 106在上电极和下电极之间。 多个单元被分组成各自包括一个或多个单元的元件，同一元件中的一个或多个单元彼此电连接。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20130256817A1
公开(公告)日：2013-10-03
申请号：US13906672
申请日：2013-05-31
Applicant: CANON KABUSHIKI KAISHA
Inventor： Takahiro Ezaki , Chienliu Chang , Yasuhiro Soeda , Kenji Tamamori
IPC: H01L29/84
CPC classification number: H01L23/5226 , B06B1/0292 , B81B2201/0257 , H01L21/76898 , H01L27/1203 , H01L29/84 , H01L2924/0002 , H01L2924/00
Abstract: An element array comprises a plurality of elements having a first electrode and a second electrode with a gap therebetween; the first electrode is separated for each of the elements by grooves, an insulating connection substrate is bonded to the first electrode, and wirings are provided from the respective first electrodes through the connection substrate to the side opposite to the first electrodes.
Abstract translation: 元件阵列包括具有第一电极和第二电极的多个元件，其间具有间隙; 通过沟槽将每个元件分离第一电极，绝缘连接衬底接合到第一电极，并且通过连接衬底从相应的第一电极到与第一电极相对的一侧提供布线。
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公开(公告)号：US12064965B2
公开(公告)日：2024-08-20
申请号：US17901033
申请日：2022-09-01
Applicant: CANON KABUSHIKI KAISHA
Inventor： Yosuke Miura , Yasuo Fujii , Yasuhiro Soeda
IPC: B41J2/14
CPC classification number: B41J2/14072
Abstract: According to the present invention, it is possible to provide an element substrate and a print head with which a decrease in yield and an increase in cost in a manufacturing process can be suppressed. For that purpose, a VH wiring line and a GNDH wiring line are provided in parallel in the same layer.
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公开(公告)号：US20220293199A1
公开(公告)日：2022-09-15
申请号：US17691291
申请日：2022-03-10
Applicant: CANON KABUSHIKI KAISHA
Inventor： Suguru Taniguchi , Toshio Negishi , Yasuhiro Soeda
Abstract: A switch is configured to switch connection between a second terminal to which a data signal is input and a memory control signal of a memory element in accordance with a switching signal included in a data signal. In write to a memory element, the switching signal switches such that the switch connects the second terminal and the memory control signal of the memory element, and a pulse signal for the write to the memory element is input via the second terminal.
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公开(公告)号：US20220288924A1
公开(公告)日：2022-09-15
申请号：US17691281
申请日：2022-03-10
Applicant: CANON KABUSHIKI KAISHA
Inventor： Soichiro Nagamochi , Toshio Negishi , Yasuhiro Soeda
Abstract: An element substrate comprises a plurality of stages of shift registers that inputs and holds a serial data signal; a latch circuit that latches the serial data held by the shift registers; a decoder circuit that inputs an output of the latch circuit and outputs a selection signal for selecting a block of the print elements or the memory elements; and a mask circuit that masks the output of the selection signal for selecting the block of the memory elements from the decoder circuit in accordance with an input bit data signal. The block of the print elements or the memory elements includes a plurality of print elements or memory elements in which one element is selected in each of the plurality of groups.
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公开(公告)号：US20220266590A1
公开(公告)日：2022-08-25
申请号：US17670325
申请日：2022-02-11
Applicant: CANON KABUSHIKI KAISHA
Inventor： Toshio Negishi , Yasuhiro Soeda
Abstract: An element substrate including a liquid discharge element, comprising a memory element capable of storing individual information of the element substrate by a write, the memory element being configured to change an impedance value by the write, a plurality of current supply elements capable of supplying a current to the memory element, and a determination unit configured to determine presence/absence of the write based on a voltage generated in the memory element by the current selectively supplied from the plurality of current supply elements, wherein the plurality of current supply elements constitute a part of a current mirror circuit and each supply the current in an amount according to a size ratio to the memory element.
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