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公开(公告)号：US11424968B1
公开(公告)日：2022-08-23
申请号：US17344323
申请日：2021-06-10
Applicant: Credo Technology Group Limited
Inventor： Junqing Sun , Fang Cai , Hung-Yi Chen , Haoli Qian
Abstract: Disclosed retimer modules and methods enable equalizer training during link speed negotiation. One illustrative retimer module includes: an analog to digital converter that uses a sampling clock to digitize a receive signal; an equalizer that converts the digitized receive signal into an equalized signal; a decision element that derives a receive symbol stream from the equalized signal; and a clock recovery module that derives the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed.
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公开(公告)号：US11356302B1
公开(公告)日：2022-06-07
申请号：US17107886
申请日：2020-11-30
Applicant: Credo Technology Group Limited
Inventor： Junqing Sun , Haoli Qian
Abstract: An illustrative digital communications method includes: filtering a receive signal to provide a filtered receive signal; deriving symbol decisions from the filtered receive signal; detecting a baud rate of the receive signal; adapting one or more coefficients of the filter if the baud rate is above a predetermined rate; and inhibiting coefficient adaptation if the baud rate is below the predetermined rate. The method may be implemented in a receiver having: a filter to convert a receive signal into a filtered receive signal; a decision element coupled to the filter to derive symbol decisions; a baud rate detector to detect a baud rate of the receive signal; and an adaptation module to adapt one or more coefficients of the filter if the baud rate is above a predetermined rate, the baud rate detector inhibiting adaptation if the baud rate is below the predetermined rate.
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公开(公告)号：US11171815B2
公开(公告)日：2021-11-09
申请号：US16748594
申请日：2020-01-21
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Junqing Sun
Abstract: In one illustrative embodiment, an equalizer includes: a shift register, an array of multipliers, an array of multiplexers, and a summer. The shift register provides receive signal samples at each tap. Each multiplier in the array multiplies one of said receive signal samples by a respective coefficient to produce a product, with at least one of said multipliers coupled to a fixed tap. Each multiplexer in the array supplies an associated one of said multipliers with a receive signal sample from a selectable tap. The summer sums the products to produce a filtered output signal. To reduce hardware requirements, coefficient multipliers may be multiplexed to a reduced set of taps, and the dynamic range of the coefficients may be increased by overlapping the sets for different multipliers. Methods of tap selection and coefficient adaptation are disclosed.
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公开(公告)号：US10728059B1
公开(公告)日：2020-07-28
申请号：US16459512
申请日：2019-07-01
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Junqing Sun , Haoli Qian
IPC: H04L25/03
Abstract: A receiver embodiment has an equalizer that includes: an array of sample and hold elements, an array of linear equalizers, and an array of decision elements. Each sample and hold element in the array periodically samples an analog receive signal with a respective phase to provide an associated held signal. Each linear equalizer in the array forms a periodically-updated weighted sum of the held signals from the array of sample and hold elements. Each decision element in the array derives at least one sequence of symbol decisions based on at least one of the periodically-updated weighted sums. The resulting sequences of symbol decisions are output in parallel.
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Patent Agency Ranking
公开(公告)号：US11347476B2
公开(公告)日：2022-05-31
申请号：US17067056
申请日：2020-10-09
Applicant: Credo Technology Group Limited
Inventor： Tianchen Luo , Junqing Sun , Haoli Qian
Abstract: Digital filters and filtering methods may employ truncation, internal rounding, and/or approximation in a summation circuit that combines multiple sets of bit products arranged by bit weight. One illustrative digital filter includes: a summation circuit coupled to multiple partial product circuits. Each partial product circuit is configured to combine bits of a filter coefficient with bits of a corresponding signal sample to produce a set of partial products. The summation circuit produces a filter output using a carry-save adder (“CSA”) tree that combines the partial products from the multiple partial product circuits into bits for two addends. The CSA tree has multiple lanes of adders, each lane being associated with a corresponding bit weight. The adders in one or more of the lanes associated with least significant bits of the filter output are approximate adders that trade accuracy for simpler implementation. In an illustrative receiver, the filter is coupled to a decision element that derives a sequence of symbol decisions.
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公开(公告)号：US11309995B2
公开(公告)日：2022-04-19
申请号：US16793746
申请日：2020-02-18
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Junqing Sun , Haoli Qian
Abstract: Digital communication transmitters, systems, and methods can introduce skew into parallel transmission channels to enhance the performance of forward error correction (FEC) decoders. One illustrative serializer-deserializer (SerDes) transmitter embodiment includes: a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks; a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion, the multiple lanes corresponding to parallel transmission channels; a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and multiple drivers, each driver configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels.
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公开(公告)号：US11231740B2
公开(公告)日：2022-01-25
申请号：US16269491
申请日：2019-02-06
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Fang Cai , Junqing Sun , Haoli Qian
Abstract: Disclosed clock recovery modules provide improved performance with only limited complexity and power requirements. In one illustrative embodiment, a clock recovery method includes: oversampling a receive signal to obtain mid-symbol interval (MSI) samples and between-symbol interval (BSI) samples; processing at least the MSI samples to obtain symbol decisions; filtering the symbol decisions to obtain BSI targets; determining a timing error based on a difference between the BSI samples and the BSI targets; and deriving from the timing error a clock signal for said oversampling.
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公开(公告)号：US20190028574A1
公开(公告)日：2019-01-24
申请号：US15654446
申请日：2017-07-19
Applicant: Credo Technology Group Limited
Inventor： Junqing Sun
IPC: H04L29/06
Abstract: An illustrative multi-lane communication method implements a hidden backchannel to communicate equalization information and/or other link-related data without impinging on the user bandwidth allocated by the relevant articles of IEEE Std 802.3. One embodiment is implemented by a transceiver: (a) receiving signals from different receive channels; (b) converting each receive channel signal into a lane of a multi-lane receive data stream via demodulation and error measurement; (c) deriving outgoing backchannel information based at least in part on the error measurement; (d) detecting alignment markers in each lane of the multi-lane receive data stream; (e) extracting incoming backchannel information from a backchannel field following each alignment marker in at least one lane of the multi-lane receive data stream; and (f) modifying the multi-lane receive data stream to obtain a modified multi-lane receive data stream by replacing backchannel fields with PCS (Physical Coding Sublayer) alignment markers, thereby creating sets of grouped PCS alignment markers in said at least one lane.
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公开(公告)号：US10069660B1
公开(公告)日：2018-09-04
申请号：US15487045
申请日：2017-04-13
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Junqing Sun , Haoli Qian , Lawrence Chi Fung Cheng
IPC: H04B1/38 , H04L25/03 , H04L7/00 , H04L1/00 , H04L12/707
Abstract: An illustrative multi-lane communication method includes: (a) receiving receive signals on different receive channels; (b) converting each of the receive signals into a lane of a multi-lane receive data stream, wherein said converting includes demodulation and error measurement; (c) determining remote pre-equalizer adaptation information based in part on the error measurement; (d) detecting alignment markers in the multi-lane receive data stream; (e) extracting local pre-equalizer adaptation information in, or proximate to, the alignment markers in the multi-lane receive data stream; (f) using the local pre-equalizer adaptation information to adjust coefficients of a local pre-equalization filter; (g) periodically inserting an alignment marker in a multi-lane transmit data stream, wherein the remote pre-equalizer adaption information is included in, or inserted proximate to, the alignment markers; and (h) transforming each lane of the multi-lane transmit data stream into a transmit signal, wherein said transforming includes modulating and applying the local pre-equalization filter.
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