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公开(公告)号：US11300613B2
公开(公告)日：2022-04-12
申请号：US17022311
申请日：2020-09-16
Applicant: Credo Technology Group Limited
Inventor： Arshan Aga , Haoli Qian , Junqing Sun , James Bartenslager
IPC: G01R31/317 , G01R29/26
Abstract: A method of assessing the ability of one or more multi-die circuit elements to tolerate the presence of jitter in intra-package. The method includes: providing a first die having a set of transmitters for digital communications, the set of transmitters comprising a first transmitter and a second transmitter; providing a second die having a set of receivers for digital communications; providing a performance monitor; coupling, using an intra-package trace, a first transmit signal from the first transmitter to a receiver of the set of receivers; coupling a second transmit signal from the second transmitter to an external pin; supplying an input signal that induces jitter in the first and second transmit signals; measuring jitter in the second transmit signal via the external pin; and determining, using the performance monitor, a performance characteristic of the second die.
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公开(公告)号：US20220021603A1
公开(公告)日：2022-01-20
申请号：US16932988
申请日：2020-07-20
Applicant: Credo Technology Group Limited
Inventor： Haoli Qian , Calvin Xiong Fang , William Brennan , Jeffrey Twombly
IPC: H04L12/707 , H04L12/26
Abstract: Active Ethernet cables that provide data path redundancy. One illustrative cable embodiment includes a first connector connected to each of a second and third connectors, the first connector including a multiplexer that couples a data stream from a selectable one of the second and third connectors to an output of the first connector. One illustrative method embodiment includes: producing from an output of a first connector a data stream from a currently selected one of multiple redundant connectors; monitoring the data stream for a fault associated with the currently selected one of multiple redundant connectors; and responsive to detecting said fault, producing from the output of the first connector a data stream from a different selected one of the multiple redundant connectors.
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公开(公告)号：US11196592B1
公开(公告)日：2021-12-07
申请号：US16937773
申请日：2020-07-24
Applicant: Credo Technology Group Limited
Inventor： Fang Cai , Junqing (Phil) Sun , Haoli Qian
Abstract: Equalization methods and equalizers employing discrete-time filters are provided with dynamic perturbation effect based adaptation. Tap coefficient values may be individually perturbed during the equalization process and the effects on residual ISI monitored to estimate gradient components or rows of a difference matrix. The gradient or difference matrix components may be assembled and filtered to obtain components suitable for calculating tap coefficient updates with reduced adaptation noise. The dynamic perturbation effect based updates may be interpolated with precalculated perturbation effect based updates to enable faster convergence with better accommodation of analog component performance changes attributable to variations in process, supply voltage, and temperature.
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公开(公告)号：US11032111B2
公开(公告)日：2021-06-08
申请号：US16552927
申请日：2019-08-27
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Junqing Sun , Haoli Qian
Abstract: An illustrative SerDes (serializer-deserializer) communications method embodiment may include a transceiver: selecting one of multiple registers to specify initial pre-equalizer coefficient values; updating the initial pre-equalizer coefficient values during a training phase; and using the updated pre-equalizer coefficient values to convey a transmit data stream. In an illustrative embodiment of a chip-to-module communications link, a port connector couples a port transceiver to a pluggable module transceiver, the pluggable module transceiver including: one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.
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公开(公告)号：US10992501B1
公开(公告)日：2021-04-27
申请号：US16836553
申请日：2020-03-31
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Junqing Sun , Haoli Qian
Abstract: An illustrative integrated receiver circuit embodiment includes: a set of analog-to-digital converters that sample a receive signal in response to staggered clock signals to provide a parallel set of sampled receive signals; an equalizer that converts the parallel set of sampled receive signals into a parallel set of equalized signals; one or more quantizers that derives symbol decisions from the parallel set of equalized signals; a digital timing circuit that generates the staggered clock signals based on the parallel set of equalized signals; and a clock skew adjustment circuit that provides a controllable skew of at least one of said staggered clock signals relative to at least one other of the staggered clock signals. A monitor circuit is included to provide a reliability indicator for the symbol decisions, as is a controller that determines a dependence of the reliability indicator on the controllable skew.
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Patent Agency Ranking
公开(公告)号：US11128497B1
公开(公告)日：2021-09-21
申请号：US16920115
申请日：2020-07-02
Applicant: Credo Technology Group Limited
Inventor： Junqing (Phil) Sun , Fang Cai , Tianchen Luo , Haoli Qian
Abstract: Decision feedback equalizers and equalization methods may employ fractional tap unrolling and/or probability-based decision threshold placement. One illustrative fractional tap unrolling equalization method embodiment includes: tracking preceding symbol decisions; converting an equalized signal into tentative symbol decisions with a precompensation unit; and selecting from the tentative symbol decisions based on the preceding symbol decisions. The precompensation unit has a decision element for each combination of a first number of speculative preceding symbols, with comparators in each decision element using a first type of symbol decision threshold that accounts for trailing intersymbol interference from the corresponding combination, and with an additional comparator in at least one of the decision elements using a second type of symbol decision threshold that accounts for trailing intersymbol interference from a second number of speculative preceding symbols, the second number being greater than the first.
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公开(公告)号：US11038602B1
公开(公告)日：2021-06-15
申请号：US16782926
申请日：2020-02-05
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Junqing Sun , Haoli Qian
Abstract: An illustrative integrated circuit and method providing on-chip jitter evaluation. One illustrative integrated circuit embodiment includes a digital receiver having a timing recovery circuit that determines a phase offset signal from estimated timing errors of previous sampling instants; and an on-chip memory that captures the phase offset signal, the on-chip memory being coupled to a processor that derives one or more jitter measurements from the phase offset signal. For initial calibration, the processor may configure the receiver for loop back operation, and thereafter the calibration values may enable evaluation of remote transmitter clock jitter.
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公开(公告)号：US11005567B2
公开(公告)日：2021-05-11
申请号：US16459491
申请日：2019-07-01
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Junqing Sun , Haoli Qian
Abstract: An illustrative SerDes receiver includes: a front-end filter, a precomputation unit, a selection element, and a controller. The front end filter converts a receive signal into a linearly-equalized signal. The precomputation unit accepts the linearly-equalized signal with or without a subtracted feedback signal, and employs a set of comparators with threshold values that depend on a first post-cursor ISI value F1, the set of comparators operating to generate a set of tentative symbol decisions. The selection element derives a selected symbol decision from each set of tentative symbol decisions, thereby deriving a sequence of symbol decisions from the receive signal. The controller constrains F1 if the receive signal uses a PAM4 signal constellation, setting F1 to equal zero if the receive signal is conveyed via a low-loss channel and to equal one if the receive signal is conveyed via a high-loss channel.
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公开(公告)号：US20200249714A1
公开(公告)日：2020-08-06
申请号：US16269491
申请日：2019-02-06
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Fang CAI , Junqing Sun , Haoli Qian
Abstract: Disclosed clock recovery modules provide improved performance with only limited complexity and power requirements. In one illustrative embodiment, a clock recovery method includes: oversampling a receive signal to obtain mid-symbol interval (MSI) samples and between-symbol interval (BSI) samples; processing at least the MSI samples to obtain symbol decisions; filtering the symbol decisions to obtain BSI targets; determining a timing error based on a difference between the BSI samples and the BSI targets; and deriving from the timing error a clock signal for said oversampling.
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公开(公告)号：US20190386851A1
公开(公告)日：2019-12-19
申请号：US16084277
申请日：2017-03-08
Applicant: Credo Technology Group Limited
Inventor： Yifei Dai , Haoli Qian , Jeff Twombly
IPC: H04L12/46 , H04L12/935 , H04L12/40 , H04L12/751 , H04B3/46
Abstract: Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.
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