公开(公告)号：US08330683B2

公开(公告)日：2012-12-11

申请号：US10962502

申请日：2004-10-13

Applicant: Hoon-Ju Chung ,  Chang-Hoon Jeon

Inventor： Hoon-Ju Chung ,  Chang-Hoon Jeon

IPC: G09G3/32

CPC classification number: G09G3/3233 ,  G09G3/2022 ,  G09G3/2029 ,  G09G3/3291 ,  G09G2300/0842

Abstract: A driving method of a flat panel display includes dividing one frame into a plurality of sub-frames, wherein each sub-frame includes an on-state time, each on-state time corresponds to a weight value, and at least one of the weight values is expressed in the form of a non-binary code; applying an on-state gate signal to a pixel in each sub-frame to turn on the pixel; and applying each bit of a data signal corresponding to each sub-frame to the pixel.

Abstract translation: 平板显示器的驱动方法包括将一帧划分成多个子帧，其中每个子帧包括接通状态时间，每个接通状态时间对应于权重值，并且至少一个权重 值以非二进制代码的形式表示; 对每个子帧中的像素施加导通状态栅极信号以使像素导通; 以及将与每个子帧相对应的数据信号的每一位应用于像素。

公开(公告)号：US20120127150A1

公开(公告)日：2012-05-24

申请号：US13297419

申请日：2011-11-16

Applicant: Keun-Choul Kim ,  Chang-Hoon Jeon

Inventor： Keun-Choul Kim ,  Chang-Hoon Jeon

IPC: G09G5/00 ,  G09G3/32

CPC classification number: G09G3/3233 ,  G09G2300/043 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861

Abstract: The present invention an organic light emitting diode display device includes a display panel having a plurality of pixel regions, a gate driving unit for driving gate lines and light emitting control lines of the display panel, a data driving unit for driving data lines of the display panel, a power supply unit for supplying first and second power signals to power lines of the display panel as well as a compensating voltage to a compensating power line, and a timing controller for controlling the gate and data driving units for displaying an image with a data voltage compensated with the compensating voltage and controlling the power supply unit to supply the compensating voltage after converting a level of the compensating voltage just before display of a first image on the display panel at an initial driving.

Abstract translation: 本发明的有机发光二极管显示装置包括具有多个像素区域的显示面板，用于驱动显示面板的栅极线和发光控制线的栅极驱动单元，用于驱动显示器的数据线的数据驱动单元 面板，用于向显示面板的电源线提供第一和第二功率信号的电源单元以及补偿电力线的补偿电压，以及用于控制用于显示图像的门和数据驱动单元的定时控制器 数据电压用补偿电压补偿，并且在初始驱动时，在显示面板上显示第一图像之前转换补偿电压的电平之后，控制电源单元提供补偿电压。

公开(公告)号：US07936021B2

公开(公告)日：2011-05-03

申请号：US11976252

申请日：2007-10-23

Applicant: Chang-Hoon Jeon ,  Satoru Yamada ,  Sang-Yeon Han ,  Jong-Man Park ,  Si-Ok Sohn

Inventor： Chang-Hoon Jeon ,  Satoru Yamada ,  Sang-Yeon Han ,  Jong-Man Park ,  Si-Ok Sohn

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/108

CPC classification number: H01L29/7851 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: In a fin field effect transistor (Fin FET) and a method of manufacturing the Fin FET, the Fin FET includes an active pattern inside which insulating layer patterns are formed, an isolation layer pattern enclosing a sidewall of the active pattern such that an opening exposing a sidewall of the active pattern located between the insulating layer patterns is formed, a gate electrode formed on the active pattern to fill the opening, impurity regions formed at portions of the active pattern adjacent to sidewalls of the gate electrode, an insulating interlayer covering the active pattern and the gate electrode and contact plugs formed through portions of the insulating interlayer and the active pattern adjacent to the sidewalls of the gate electrode such that the contact plug makes contact with the impurity region.

Abstract translation: 在翅片场效应晶体管（Fin FET）和制造Fin FET的方法中，Fin FET包括其中形成绝缘层图案的有源图案，包围有源图案的侧壁的隔离层图案，使得开口露出 形成位于绝缘层图案之间的有源图案的侧壁，形成在有源图案上以填充开口的栅电极，形成在与栅电极的侧壁相邻的有源图案的部分处的杂质区，覆盖 有源图案和通过绝缘夹层的一部分和与栅电极的侧壁相邻的有源图案形成的栅电极和接触插塞，使得接触插塞与杂质区接触。

公开(公告)号：US20100140692A1

公开(公告)日：2010-06-10

申请号：US12705011

申请日：2010-02-12

Applicant: Se-Myeong Jang ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Hyun-Ju Sung ,  Hui-Jung Kim ,  Chang-Hoon Jeon

Inventor： Se-Myeong Jang ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Hyun-Ju Sung ,  Hui-Jung Kim ,  Chang-Hoon Jeon

IPC: H01L29/78

CPC classification number: H01L27/105 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/1052

Abstract: In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region.

Abstract translation: 在制造具有多个沟道晶体管和由此制造的半导体器件的半导体器件的方法中，半导体器件包括布置在半导体衬底内并限定第一区域的隔离区域。 与第一区域自对准并且彼此间隔开的多个半导体柱设置在第一区域内，并且每个半导体柱在其中具有至少一个凹陷区域。 至少一个栅极结构可以设置在穿过半导体柱并且延伸到隔离区上的凹陷区域之间。

公开(公告)号：US07691689B2

公开(公告)日：2010-04-06

申请号：US11486343

申请日：2006-07-13

Applicant: Se-Myeong Jang ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Hyun-Ju Sung ,  Hui-Jung Kim ,  Chang-Hoon Jeon

Inventor： Se-Myeong Jang ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Hyun-Ju Sung ,  Hui-Jung Kim ,  Chang-Hoon Jeon

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/36

CPC classification number: H01L27/105 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/1052

Abstract: In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region.

Abstract translation: 在制造具有多个沟道晶体管和由此制造的半导体器件的半导体器件的方法中，半导体器件包括设置在半导体衬底内并限定第一区域的隔离区域。 与第一区域自对准并且彼此间隔开的多个半导体柱设置在第一区域内，并且每个半导体柱在其中具有至少一个凹陷区域。 至少一个栅极结构可以设置在穿过半导体柱并且延伸到隔离区上的凹陷区域之间。