公开(公告)号：US5430673A

公开(公告)日：1995-07-04

申请号：US92189

申请日：1993-07-14

申请人： Gary Hong ,  Chen-Chiu Hsue

发明人： Gary Hong ,  Chen-Chiu Hsue

IPC分类号： H01L27/112 ,  H01L27/10 ,  H01L29/78

CPC分类号： H01L27/112

摘要： A ROM array comprises orthogal sets of buried bit lines and polysilicon wordlines. The buried bit lines comprise trenches with insulating material on the side walls, the trenches then being filled with polysilicon. Theis reduces bit line sheet resistance and increases the punch through voltage between adjacent bit lines.

摘要翻译： ROM阵列包括掩埋位线和多晶硅字线的正整组。 掩埋位线包括在侧壁上具有绝缘材料的沟槽，然后沟槽填充有多晶硅。 它可以减少位线电阻，并增加相邻位线之间的穿通电压。

公开(公告)号：US5380675A

公开(公告)日：1995-01-10

申请号：US210933

申请日：1994-03-21

申请人： Chen-Chiu Hsue ,  Gary Hong

发明人： Chen-Chiu Hsue ,  Gary Hong

IPC分类号： H01L21/8242 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852

摘要： A method for fabricating an array of closely spaced storage capacitors, with increased capacitance, on a dynamic random access memory (DRAM) chip is achieved. The capacitors are increased in capacitance by minimizing the spacings between the adjacent bottom electrodes of the storage capacitors and, thereby increases the area of the capacitor electrodes. A local oxidation techniques is used to form a silicon oxide etch mask, on the bottom electrode polysilicon layer, that extends laterally under a patterned silicon nitride masking layer. This encroachment of the silicon oxide under the patterned silicon nitride layer reduces the spacing between electrodes, exceeding the resolution limits of the photoresist. The silicon nitride is removed and the silicon oxide mask is used to pattern the polysilicon layer forming an array of closely spaced polysilicon bottom electrodes. The silicon oxide is removed and an inter-electrode dielectric is deposited on the array of bottom electrode. A second doped polysilicon layer is then deposited to form the top electrode and complete the DRAM capacitors.

摘要翻译： 实现了在动态随机存取存储器（DRAM）芯片上制造具有增加的电容的紧密间隔的存储电容器阵列的方法。 通过最小化存储电容器的相邻底部电极之间的间隔，电容器增加电容，从而增加电容器电极的面积。 使用局部氧化技术在底部电极多晶硅层上形成在图案化的氮化硅掩蔽层下横向延伸的氧化硅蚀刻掩模。 氧化硅在图案化氮化硅层下的这种侵蚀减少了电极之间的间隔，超过了光致抗蚀剂的分辨率极限。 去除氮化硅并且使用氧化硅掩模来对形成紧密间隔的多晶硅底部电极的阵列的多晶硅层进行图案化。 去除氧化硅并且在底部电极阵列上沉积电极间电介质。 然后沉积第二掺杂多晶硅层以形成顶部电极并完成DRAM电容器。

公开(公告)号：US5882970A

公开(公告)日：1999-03-16

申请号：US552428

申请日：1995-11-03

申请人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong ,  Chen-Chiu Hsue

发明人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong ,  Chen-Chiu Hsue

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A flash memory cell is fabricated by forming a lightly-doped region with only an implantation procedure to avoid lateral diffusion resulting from an increased overlap between the source region and gate as well as a short channel effect, while surrounding the source region with the lightly-doped region to thereby increase the breakdown voltage between the source region and the substrate.

摘要翻译： 闪存单元是通过仅通过注入步骤形成轻掺杂区域来制造的，以避免由于源区和栅极之间的重叠增加而产生的横向扩散以及短沟道效应，同时围绕源极区域， 从而增加源极区域和衬底之间的击穿电压。

公开(公告)号：US5849625A

公开(公告)日：1998-12-15

申请号：US807885

申请日：1997-02-26

申请人： Chen-Chiu Hsue ,  Gary Hong

发明人： Chen-Chiu Hsue ,  Gary Hong

IPC分类号： H01L21/762 ,  H01L2/76

CPC分类号： H01L21/76205 ,  H01L21/76237

摘要： A process for fabricating an improved planar field oxide (FOX) structure on a silicon substrate was achieved. The process involves forming recessed areas in the silicon substrate where the field oxide is require. A thin silicon oxide is formed on the surface of the recessed areas as a nucleation layer and then a thicker silicon oxide layer is selectively deposited in the recess areas by Liquid Phase Deposition (LPD). The planar FOX structure formed by LPD can be used in conjunction with a FOX structure formed by the conventional LOCal Oxidation of Silicon (LOCOS) process on the same substrate. The planar field oxide formed by LPD eliminates the bird beak structure and the lateral diffusion of the channel stop implant commonly associated with the LOCOS structure.

摘要翻译： 实现了在硅衬底上制造改进的平面场氧化物（FOX）结构的工艺。 该方法包括在需要场氧化物的硅衬底中形成凹陷区域。 在凹陷区域的表面上形成薄的氧化硅作为成核层，然后通过液相沉积（LPD）在凹陷区域中选择性地沉积更厚的氧化硅层。 由LPD形成的平面FOX结构可以与在同一衬底上通过常规的局部氧化硅（LOCOS）工艺形成的FOX结构结合使用。 由LPD形成的平面场氧化物消除了鸟喙结构和通常与LOCOS结构相关联的通道停止植入物的横向扩散。

公开(公告)号：US5716884A

公开(公告)日：1998-02-10

申请号：US682403

申请日：1996-07-17

申请人： Chen-Chiu Hsue ,  Gary Hong ,  Ming-Tzong Yang

发明人： Chen-Chiu Hsue ,  Gary Hong ,  Ming-Tzong Yang

IPC分类号： H01L21/8242

CPC分类号： H01L27/10852

摘要： A method for fabricating a capacitor having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses in the bottom electrode forming inter-digitized fin-shaped top and bottom capacitor electrodes and completing a dynamic random access memory (DRAM) cell.

摘要翻译： 实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造具有鳍状电极的电容器的方法。 电容器制造在具有有源器件区域的硅衬底上。 器件区域包含一个金属氧化物半导体场效应晶体管（MOSFET），其中一个电容器对准器件区域中与MOSFET的源极/漏极对准并接触。 通过在存储电容器区域和凹陷交替层上形成多层绝缘体结构，然后使用该形式作为形成多晶硅鳍状底部电容器电极的模具，电容器增加电容。 去除剩余的多层模具，并且在底部电极上沉​​积高介电常数绝缘体作为电极间电介质。 顶部电容器电极通过沉积掺杂多晶硅层而形成，掺杂多晶硅层还填充底部电极中的凹陷，形成数字化的鳍状顶部和底部电容器电极，并完成动态随机存取存储器（DRAM）单元。

公开(公告)号：US5646436A

公开(公告)日：1997-07-08

申请号：US536934

申请日：1995-09-29

申请人： Gary Hong ,  Chen-Chiu Hsue ,  Chen-Hui Chung

发明人： Gary Hong ,  Chen-Chiu Hsue ,  Chen-Hui Chung

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/265

CPC分类号： H01L27/1126 ,  H01L27/112

摘要： A Read-Only Memory (ROM) device produced by self-aligned implantation. First, a non-coded mask ROM with a silicon substrate, a plurality of bit-lines formed in the substrate, a gate oxide layer formed on the bit-lines, and a plurality of word-lines formed on the gate oxide, which together form arrays of memory cells, is provided. Next, an aligning layer is formed above the word-lines. A photoresist is thereafter coated on the surface of the aligning layer. Then, portions of the photoresist not covered by a mask pattern are etched away to the aligning layer so as to provide openings exposing portions of the memory cells that will be programmed to operate in a first conduction state. Portions of the aligning layer exposed through the openings are then removed, after which impurities are implanted through the openings and into the substrate to enable the memory cells that are to operate in the first conduction state, and leave other non-programmed memory cells operating in a second conduction state.

摘要翻译： 通过自对准植入制造的只读存储器（ROM）器件。 首先，具有硅衬底的非编码掩模ROM，在衬底中形成的多个位线，形成在位线上的栅极氧化层，以及形成在栅极氧化物上的多个字线，其一起 提供了存储单元的阵列。 接下来，在字线上形成对准层。 然后将光致抗蚀剂涂覆在对准层的表面上。 然后，未被掩模图案覆盖的部分光致抗蚀剂被蚀刻掉到对准层上，以便提供露出将被编程为在第一导通状态下操作的存储单元部分的开口。 然后去除通过开口暴露的对准层的部分，之后通过开口注入杂质并进入衬底，以使得能够在第一导通状态下操作的存储器单元，并且使其他非编程存储器单元在 第二导通状态。

公开(公告)号：US5494839A

公开(公告)日：1996-02-27

申请号：US237352

申请日：1994-05-03

申请人： Gary Hong ,  Chen-Chiu Hsue

发明人： Gary Hong ,  Chen-Chiu Hsue

IPC分类号： H01L21/027 ,  H01L21/3213 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L21/0274 ,  H01L21/32139 ,  Y10S438/943

摘要： A dual photo-resist process for fabricating capacitor plates of a DRAM is disclosed including the step of forming a capacitor on a semiconductor IC surface. A first plurality of photo-resist regions which are separated from each other by spaces are then formed on the capacitor plate layer. At least one second photo-resist region is then formed on the capacitor plate layer which partially fills a space between, and is adjacent to one of, two of the first photo-resist regions. The capacitor plate layer is then etched below the spaces between the first and second photo-resist regions to form a plurality of individual capacitor plates including one capacitor plate for each DRAM cell.

摘要翻译： 公开了一种用于制造DRAM的电容器板的双光阻工艺，包括在半导体IC表面上形成电容器的步骤。 然后在电容器板层上形成通过间隔彼此分开的第一多个光致抗蚀剂区域。 然后在电容器板层上形成至少一个第二光刻抗蚀剂区域，其部分地填充两个第一光致抗蚀剂区域之间的空间，并且邻近其中之一。 然后在第一和第二光致抗蚀剂区域之间的空间下方蚀刻电容器板层，以形成多个单独的电容器板，其包括用于每个DRAM单元的一个电容器板。

公开(公告)号：US5457061A

公开(公告)日：1995-10-10

申请号：US275269

申请日：1994-07-15

申请人： Gary Hong ,  Chen-Chiu Hsue

发明人： Gary Hong ,  Chen-Chiu Hsue

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L21/266

CPC分类号： H01L29/66825 ,  H01L27/11517

摘要： A method for forming, and a resultant structure of, a top floating gate FLASH EEPROM cell are described. There is a first insulating structure over a silicon substrate, whereby the first insulating structure is a gate oxide. A first conductive structure is formed over the first insulating structure, whereby the first conductive structure is a control gate. There is a first insulating layer over the surfaces of the first conductive structure, whereby the first insulating layer is an interpoly dielectric. There is a second conductive structure formed over the first insulating layer and over a portion of the silicon substrate adjacent to the first insulating structure, whereby the second conductive structure is a floating gate. A second insulating layer is formed between the silicon substrate and the second conductive structure, whereby the second insulating layer is a tunnel oxide. Active regions in the silicon substrate, implanted with a conductivity-imparting dopant, are formed under the second insulating layer but are horizontally a distance from the first insulating structure.

摘要翻译： 描述了用于形成顶部浮置栅极FLASH EEPROM单元的方法和结果。 在硅衬底上存在第一绝缘结构，由此第一绝缘结构是栅极氧化物。 在第一绝缘结构上形成第一导电结构，由此第一导电结构是控制栅极。 在第一导电结构的表面上存在第一绝缘层，由此第一绝缘层是互聚电介质。 在第一绝缘层上形成第二导电结构，并且与第一绝缘结构相邻的硅衬底的一部分上方形成第二导电结构，由此第二导电结构是浮栅。 在硅衬底和第二导电结构之间形成第二绝缘层，由此第二绝缘层是隧道氧化物。 在第二绝缘层的下方形成硅衬底中注入导电性赋予剂的有源区，但与水平方向距离第一绝缘结构。

公开(公告)号：US5578857A

公开(公告)日：1996-11-26

申请号：US349432

申请日：1994-12-05

申请人： Gary Hong ,  Ming-Tzong Yang ,  Chen-Chiu Hsue

发明人： Gary Hong ,  Ming-Tzong Yang ,  Chen-Chiu Hsue

IPC分类号： H01L21/8246 ,  H01L29/76

CPC分类号： H01L27/1126

摘要： In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.

摘要翻译： 根据本发明，双重多晶法用于将相同硅区上的掩埋位线ROM的存储密度加倍。 特别地，减小字线间距以在垂直于字线的方向上增加单元密度。 本发明采用自对准方法进行ROM码植入和通过化学机械抛光（CMP）进行多平面化，以实现自对准双多重字线结构。

公开(公告)号：US5436186A

公开(公告)日：1995-07-25

申请号：US231516

申请日：1994-04-22

申请人： Chen-Chiu Hsue ,  Gary Hong ,  Ming-Tzong Yang

发明人： Chen-Chiu Hsue ,  Gary Hong ,  Ming-Tzong Yang

IPC分类号： H01L21/8242

CPC分类号： H01L27/10852

摘要： A method for fabricating a capacitors having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses in the bottom electrode forming an interdigitized fin-shaped top and bottom capacitor electrodes and completing a dynamic random access memory (DRAM) cell.

摘要翻译： 实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造具有鳍状电极的电容器的方法。 电容器制造在具有有源器件区域的硅衬底上。 器件区域包含一个金属氧化物半导体场效应晶体管（MOSFET），其中一个电容器对准器件区域中与MOSFET的源极/漏极对准并接触。 通过在存储电容器区域和凹陷交替层上形成多层绝缘体结构，然后使用该形式作为形成多晶硅鳍状底部电容器电极的模具，电容器增加电容。 去除剩余的多层模具，并且在底部电极上沉​​积高介电常数绝缘体作为电极间电介质。 顶部电容器电极通过沉积掺杂的多晶硅层而形成，掺杂多晶硅层还填充底部电极中的凹部，形成交错的鳍状顶部和底部电容器电极并完成动态随机存取存储器（DRAM）单元。