公开(公告)号：US5882970A

公开(公告)日：1999-03-16

申请号：US552428

申请日：1995-11-03

申请人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong ,  Chen-Chiu Hsue

发明人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong ,  Chen-Chiu Hsue

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A flash memory cell is fabricated by forming a lightly-doped region with only an implantation procedure to avoid lateral diffusion resulting from an increased overlap between the source region and gate as well as a short channel effect, while surrounding the source region with the lightly-doped region to thereby increase the breakdown voltage between the source region and the substrate.

摘要翻译： 闪存单元是通过仅通过注入步骤形成轻掺杂区域来制造的，以避免由于源区和栅极之间的重叠增加而产生的横向扩散以及短沟道效应，同时围绕源极区域， 从而增加源极区域和衬底之间的击穿电压。

公开(公告)号：US5646056A

公开(公告)日：1997-07-08

申请号：US540776

申请日：1995-10-11

申请人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong

发明人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L21/265

CPC分类号： H01L29/456 ,  H01L29/41775 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/49

摘要： In a method for fabricating a ULSI MOSFET, an additional polysilicon layer is used to form polysilicon/metal compound metal contacts on source and drain regions and a gate so as to avoid leakage current and short channel effect problems.

摘要翻译： 在制造ULSI MOSFET的方法中，使用附加的多晶硅层在源极和漏极区域和栅极上形成多晶硅/金属复合金属触点，以避免漏电流和短沟道效应问题。

公开(公告)号：US20070018258A1

公开(公告)日：2007-01-25

申请号：US11160657

申请日：2005-07-05

申请人： Anchor Chen ,  Chih-Hung Lin ,  Hwi-Huang Chen ,  Jih-Wei Liou ,  Chin-Hung Liu ,  Ming-Tsung Tung ,  Chien-Ming Lin ,  Jung-Ching CHEN

发明人： Anchor Chen ,  Chih-Hung Lin ,  Hwi-Huang Chen ,  Jih-Wei Liou ,  Chin-Hung Liu ,  Ming-Tsung Tung ,  Chien-Ming Lin ,  Jung-Ching CHEN

IPC分类号： H01L29/76

CPC分类号： H01L29/0692 ,  H01L29/0638 ,  H01L29/1041 ,  H01L29/7833

摘要： A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.

摘要翻译： 高压器件结构包括设置在半导体衬底上的高电压器件。 半导体包括有源区和隔离区，高压器件设置在有源区中。 高压器件结构包括第一导电类型的源极扩散区域，第一导电类型的漏极区域和比源极扩散区域和漏极扩散区域更长的栅极，以在第二导电类型的两侧形成备用区域 大门。 隔离区域在有源区域之外并且围绕有源区域。 在隔离区域中，设置第二导电型隔离离子注入区域和延伸离子注入区域，以防止在源极扩散区域和漏极扩散区域之间产生寄生电流。

公开(公告)号：US07244975B2

公开(公告)日：2007-07-17

申请号：US11160657

申请日：2005-07-05

申请人： Anchor Chen ,  Chih-Hung Lin ,  Hwi-Huang Chen ,  Jih-Wei Liou ,  Chin-Hung Liu ,  Ming-Tsung Tung ,  Chien-Ming Lin ,  Jung-Ching Chen

发明人： Anchor Chen ,  Chih-Hung Lin ,  Hwi-Huang Chen ,  Jih-Wei Liou ,  Chin-Hung Liu ,  Ming-Tsung Tung ,  Chien-Ming Lin ,  Jung-Ching Chen

IPC分类号： H01L27/10 ,  H01L29/739 ,  H01L29/73 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/0692 ,  H01L29/0638 ,  H01L29/1041 ,  H01L29/7833

摘要： A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.

摘要翻译： 高压器件结构包括设置在半导体衬底上的高电压器件。 半导体包括有源区和隔离区，高压器件设置在有源区中。 高电压器件结构包括第一导电类型的源极扩散区域，第一导电类型的漏极区域和比源极扩散区域和漏极扩散区域更长的栅极，以在第二导电类型的两侧形成备用区域 大门。 隔离区域在有源区域之外并且围绕有源区域。 在隔离区域中，设置第二导电型隔离离子注入区域和延伸离子注入区域，以防止在源极扩散区域和漏极扩散区域之间产生寄生电流。

公开(公告)号：US5716874A

公开(公告)日：1998-02-10

申请号：US603248

申请日：1996-02-20

申请人： Joe Ko ,  Gary Hong ,  Chih-Hung Lin

发明人： Joe Ko ,  Gary Hong ,  Chih-Hung Lin

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method of fabricating an EPROM memory increases a coupling ratio and reduces lateral diffusion by forming a gate oxide layer and a coupling insulator individually. A substrate is provided with a field oxide layer to isolate a predetermined active area. A gate oxide layer is formed on the substrate. On the field oxide layer and the gate oxide layer, a polysilicon layer is deposited and defined, whereby a portion of this polysilicon layer and gate oxide layer form a gate electrode. Using the gate electrode as a mask, the substrate is implanted with impurities to provide source and drain electrodes. A dielectric layer is formed on polysilicon layer. A contact window (via) is formed in a predetermined area of dielectric layer. An insulator is deposited and defined by etching, on dielectric layer and the contact window. On the insulator and dielectric layer, a metal contact layer is deposited and defined to cover the insulator.

摘要翻译： 制造EPROM存储器的方法通过单独形成栅极氧化物层和耦合绝缘体来增加耦合比并减小横向扩散。 衬底设置有场氧化物层以隔离预定的有效面积。 在衬底上形成栅氧化层。 在场氧化物层和栅极氧化物层上沉积并限定多晶硅层，由此该多晶硅层和栅极氧化物层的一部分形成栅电极。 使用栅电极作为掩模，衬底被注入杂质以提供源极和漏极。 介电层形成在多晶硅层上。 在电介质层的预定区域中形成接触窗（通孔）。 通过在电介质层和接触窗上进行蚀刻来沉积并限定绝缘体。 在绝缘体和电介质层上，沉积和限定金属接触层以覆盖绝缘体。

公开(公告)号：US5726081A

公开(公告)日：1998-03-10

申请号：US544659

申请日：1995-10-18

申请人： Chih-Hung Lin ,  Gary Hong

发明人： Chih-Hung Lin ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L29/41783 ,  H01L29/458 ,  H01L29/4908

摘要： In a method for fabricating a ULSI MOSFET with SOI structure, an additional polysilicon layer is used to form polysilicon/metal compound metal contacts on source and drain regions and a gate so as to avoid leakage current and short channel effect problems.

摘要翻译： 在制造具有SOI结构的ULSI MOSFET的方法中，使用附加多晶硅层在源极和漏极区域和栅极上形成多晶硅/金属复合金属触点，以避免漏电流和短沟道效应问题。

公开(公告)号：US6001707A

公开(公告)日：1999-12-14

申请号：US241760

申请日：1999-02-01

申请人： Chih-Hung Lin ,  Gary Hong

发明人： Chih-Hung Lin ,  Gary Hong

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/76237

摘要： A method for forming a shallow trench isolation structure in a substrate includes the steps of forming a doped region around the future top corner regions of a trench. The concentration of dopants inside the doped region increases towards the substrate surface. Thereafter, a trench is formed in the substrate, and then a thermal oxidation operation is carried out. Utilizing the higher oxidizing rate for doped substrate relative to an undoped region, the upper corners of the trench become rounded corners. Subsequently, a liner oxide layer is formed over the substrate surface inside the trench using conventional methods. Finally, insulating material is deposited into the trench to form a trench isolation structure.

摘要翻译： 在衬底中形成浅沟槽隔离结构的方法包括以下步骤：在沟槽的未来顶角区域周围形成掺杂区域。 掺杂区内掺杂剂的浓度朝向衬底表面增加。 之后，在衬底中形成沟槽，然后进行热氧化操作。 利用掺杂衬底相对于未掺杂区域的较高氧化速率，沟槽的上角变成圆角。 随后，使用常规方法在沟槽内的衬底表面上形成衬里氧化物层。 最后，将绝缘材料沉积到沟槽中以形成沟槽隔离结构。

公开(公告)号：USD919403S1

公开(公告)日：2021-05-18

申请号：US29715575

申请日：2019-12-03

申请人： Chih-Hung Lin

设计人： Chih-Hung Lin

公开(公告)号：US20190023480A1

公开(公告)日：2019-01-24

申请号：US15654822

申请日：2017-07-20

申请人： Chih-Hung Lin

发明人： Chih-Hung Lin

IPC分类号： B65D81/38 ,  B65D81/34 ,  B65D30/08 ,  B29C65/00

摘要： A foldable cushion bag includes a main body and a handling unit. The main body includes a bottom wall and a sleeve wall jointed to the bottom wall. The bottom wall and the sleeve wall form a first heat sealed joint therebetween and cooperatively define a space for receiving a bottle. Each of the bottom and sleeve walls includes a multilayered structure having an outermost protecting layer, a first adhesive layer, a heat sealing layer, a second adhesive layer and an innermost cushion layer in that order. The handling unit is connected to the sleeve wall and opposite to the bottom wall. The handling unit is formed with a gripping hole.

公开(公告)号：USD722847S1

公开(公告)日：2015-02-24

申请号：US29490850

申请日：2014-05-14

申请人： Chih-Hung Lin

设计人： Chih-Hung Lin