公开(公告)号：US20080268612A1

公开(公告)日：2008-10-30

申请号：US11962611

申请日：2007-12-21

申请人： Whee Won Cho ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Suk Joong Kim ,  Jong Hye Cho

发明人： Whee Won Cho ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Suk Joong Kim ,  Jong Hye Cho

IPC分类号： H01L21/762

CPC分类号： H01L21/76232

摘要： The present invention discloses to a method of forming an isolation layer in a semiconductor device. In particular, the method of forming an isolation layer in a semiconductor device of the present invention comprises the steps of providing a semiconductor substrate on which a trench is formed; forming spacers on side walls of the trench; forming a first insulating layer to fill a portion of the trench such that a deposition rate on the semiconductor substrate which is a bottom surface of the trench and exposed between the spacers is higher than that on a surface of the space; and forming a second insulating layer on the first insulating layer so as to fill the trench with the second insulating layer. An O3-TEOS layer on the exposed semiconductor substrate which is a bottom surface of the trench is grown faster than that on a surface of the spacer formed of an oxide layer or a nitride layer to prevent the O3-TEOS layers grown on the side walls from coming into contact with each other, and so it is possible to inhibit a generation of a seam and to enhance a gap-filling characteristic for the trench.

摘要翻译： 本发明公开了一种在半导体器件中形成隔离层的方法。 特别地，本发明的半导体器件中形成隔离层的方法包括以下步骤：提供其上形成有沟槽的半导体衬底; 在沟槽的侧壁上形成间隔物; 形成第一绝缘层以填充所述沟槽的一部分，使得作为所述沟槽的底表面并暴露在所述间隔物之间​​的所述半导体衬底上的沉积速率高于所述空间的表面上的沉积速率; 以及在所述第一绝缘层上形成第二绝缘层以便用所述第二绝缘层填充所述沟槽。 作为沟槽底面的暴露的半导体衬底上的O 3 -TOS层比由氧化物层或氮化物层形成的间隔物的表面上生长得快，以防止O 在侧壁上生长的3层以上的层彼此接触，因此可以抑制接缝的产生并且增强沟槽的间隙填充特性。

公开(公告)号：US20080102622A1

公开(公告)日：2008-05-01

申请号：US11647088

申请日：2006-12-27

申请人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho ,  Seong Hwan Myung

发明人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho ,  Seong Hwan Myung

IPC分类号： H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/3212

摘要： A method of forming a metal line in a semiconductor device, including the steps of forming a metal line in a semiconductor device in which dummy patterns are formed on a dummy region by using non-metal material when a metal line is formed through a damascene process to prevent a formation of an oxide layer on an aluminum layer caused by a slurry and cleaning solution used in the chemical mechanical polishing (CMP) process and carry out an uniform polishing process, whereby it is possible to prevent a digging phenomenon on a metal layer from being generated.

摘要翻译： 一种在半导体器件中形成金属线的方法，包括以下步骤：在通过镶嵌工艺形成金属线时，通过使用非金属材料在虚拟区域上形成虚拟图案的半导体器件中形成金属线 以防止由化学机械抛光（CMP）工艺中使用的浆料和清洗液在铝层上形成氧化物层，并进行均匀的抛光工艺，从而可以防止在金属层上的挖掘现象 从被生成。

公开(公告)号：US06579789B2

公开(公告)日：2003-06-17

申请号：US09880055

申请日：2001-06-14

申请人： Cheol Mo Jeong

发明人： Cheol Mo Jeong

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/28518 ,  H01L23/485 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the method for fabricating a metal wiring, an insulation film is formed on a semiconductor substrate. The insulation film has a contact hole exposing the semiconductor substrate. A Ti—Si film is formed over the silicon substrate, and a Ti—Si—N film is formed on the Ti—Si film. The contact hole is then filled by depositing copper on the Ti—Si—N film, and a silicon nitride film is formed over the silicon substrate.

公开(公告)号：US07892919B2

公开(公告)日：2011-02-22

申请号：US12163328

申请日：2008-06-27

申请人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho

发明人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho

IPC分类号： H01L21/8242

CPC分类号： H01L21/76232

摘要： The invention discloses a method of forming an isolation layer in a semiconductor device. The method includes providing a semiconductor substrate having a trench formed therein; forming a first insulating layer in the trench; and forming a densified second insulating layer on the first insulating layer. In the above method, a void is not generated in the isolation layer so a bending phenomenon of an active region can be reduced or prevented to improve an electrical characteristic of the semiconductor.

摘要翻译： 本发明公开了一种在半导体器件中形成隔离层的方法。 该方法包括提供其中形成有沟槽的半导体衬底; 在沟槽中形成第一绝缘层; 以及在所述第一绝缘层上形成致密的第二绝缘层。 在上述方法中，在隔离层中不会产生空隙，因此可以减少或防止有源区的弯曲现象来改善半导体的电特性。

公开(公告)号：US20100304549A1

公开(公告)日：2010-12-02

申请号：US12815317

申请日：2010-06-14

申请人： Cha Deok DONG ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

发明人： Cha Deok DONG ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.

摘要翻译： 形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。 每个第一沟槽的侧壁和底表面被自由基氧化过程氧化以形成第一氧化物层。 在每个第一沟槽的侧壁上形成防氧化间隔物。 第二沟槽形成在对应的第一沟槽下方的隔离区域中，其中每个第二沟槽比相应的第一沟槽更窄和更深。 第二沟槽填充有第二氧化物层。 第一沟槽填充有绝缘层。

公开(公告)号：US20090179329A1

公开(公告)日：2009-07-16

申请号：US12345611

申请日：2008-12-29

申请人： Cheol Mo Jeong ,  Eun Soo Kim ,  Seung Hee Hong

发明人： Cheol Mo Jeong ,  Eun Soo Kim ,  Seung Hee Hong

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to semiconductor devices and a method of fabricating the same. According to a method of manufacturing semiconductor devices, there is first provided a semiconductor substrate in which a first pre-metal dielectric layer including trenches is formed. A diffusion barrier layer is formed on the entire surface including the trenches. A metal layer is formed on the diffusion barrier layer including the trenches, thereby gap-filling the trenches. A polish etching process is performed on the metal layer and the diffusion barrier layer so that the diffusion barrier layer and the metal layer remain within the trenches. An etching process of lowering a height of the metal layer is performed in order to increase a distance between metal lines. A capping layer is formed on the entire surface including exposed sidewalls of the first pre-metal dielectric layer. A second pre-metal dielectric layer is formed over the capping layer.

摘要翻译： 本发明涉及半导体器件及其制造方法。 根据制造半导体器件的方法，首先提供其中形成包括沟槽的第一预金属电介质层的半导体衬底。 在包括沟槽的整个表面上形成扩散阻挡层。 在包括沟槽的扩散阻挡层上形成金属层，从而间隙填充沟槽。 在金属层和扩散阻挡层上进行抛光蚀刻工艺，使得扩散阻挡层和金属层保留在沟槽内。 执行降低金属层的高度的蚀刻工艺，以增加金属线之间的距离。 在包括第一预金属介电层的暴露的侧壁的整个表面上形成覆盖层。 在覆盖层上方形成第二预金属介电层。

公开(公告)号：US07517793B2

公开(公告)日：2009-04-14

申请号：US11753543

申请日：2007-05-24

申请人： Seung Hee Hong ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Soo Kim

发明人： Seung Hee Hong ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Soo Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/28562 ,  H01L21/32131 ,  H01L21/76879 ,  H01L21/76882

摘要： A method of forming a metal wire in a semiconductor device includes performing a first etching process on an insulating layer formed on a semiconductor substrate to form a trench and an insulating layer pattern, the insulating layer pattern defining the trench. A barrier metal layer is formed over the insulating layer pattern and the trench. A second etching process is performed on the barrier metal layer to expose upper corners of the trench while leaving the trench substantially covered with the barrier metal layer. A metal layer is formed over the barrier metal layer in the trench. A heat treatment process is performed for reflowing the metal layer. The metal layer is planarized.

摘要翻译： 在半导体器件中形成金属线的方法包括对形成在半导体衬底上的绝缘层进行第一蚀刻工艺以形成沟槽和绝缘层图案，绝缘层图案限定沟槽。 在绝缘层图案和沟槽之上形成阻挡金属层。 在阻挡金属层上进行第二蚀刻工艺以暴露沟槽的上角，同时留下基本上被阻挡金属层覆盖的沟槽。 在沟槽中的阻挡金属层的上方形成有金属层。 进行用于回流金属层的热处理工艺。 金属层被平坦化。

公开(公告)号：US07504333B2

公开(公告)日：2009-03-17

申请号：US11614082

申请日：2006-12-21

申请人： Cheol Mo Jeong ,  Whee Won Cho ,  Eun Soo Kim ,  Seung Hee Hong

发明人： Cheol Mo Jeong ,  Whee Won Cho ,  Eun Soo Kim ,  Seung Hee Hong

IPC分类号： H01L21/20

CPC分类号： H01L21/76864 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/76846 ,  H01L21/76876

摘要： A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.

摘要翻译： 形成半导体器件的导电结构（例如位线）的方法包括在形成结构的半导体衬底上形成阻挡金属层。 在阻挡金属层上形成非晶氮化钛层。 在包含硼气体的气氛下，在非晶态氮化钛层上形成钨种子层。 在钨籽晶层上形成钨层，形成位线。

公开(公告)号：US20080105983A1

公开(公告)日：2008-05-08

申请号：US11604484

申请日：2006-11-27

申请人： Cheol Mo Jeong ,  Seong Hwan Myung ,  Eun Soo Kim ,  Suk Joong Kim

发明人： Cheol Mo Jeong ,  Seong Hwan Myung ,  Eun Soo Kim ,  Suk Joong Kim

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/53266 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76876 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier metal layer are formed and on a top surface of an insulating layer over a semiconductor substrate on the bottom surface of trenches formed in the insulating layer. The third barrier metal layer is formed on sidewalls of trenches. The metal line gap-fills the trenches. In a method of forming a metal line of a semiconductor device, trenches are formed within an insulating layer over a semiconductor substrate. A first barrier metal layer and a second barrier metal layer are formed on a bottom surface of the trenches and on a top surface of the insulating layer. A third barrier metal layer is formed on sidewalls of trenches. A metal line gap-fills the trenches.

摘要翻译： 半导体器件包括第一阻挡金属层和第二阻挡金属层，第三阻挡金属层和金属线。 第一阻挡金属层和第二阻挡金属层形成在半导体衬底上的形成在绝缘层的沟槽的底表面上的绝缘层的顶表面上。 第三阻挡金属层形成在沟槽的侧壁上。 金属线间隙填充沟槽。 在形成半导体器件的金属线的方法中，在半导体衬底上的绝缘层内形成沟槽。 第一阻挡金属层和第二阻挡金属层形成在沟槽的底表面和绝缘层的顶表面上。 第三阻挡金属层形成在沟槽的侧壁上。 金属线间隙填充沟槽。

公开(公告)号：US20080003754A1

公开(公告)日：2008-01-03

申请号：US11646777

申请日：2006-12-28

申请人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung

发明人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.

摘要翻译： 一种形成闪速存储器件的栅极的方法，包括以下步骤：在半导体衬底上形成栅极并在栅极的整个表面上形成氧化物层，在间隔物的氧化物层的侧壁上形成氮化物层 形成，进行抛光处理使得栅极的顶表面露出，然后剥离氮化物层以形成开口，在开口的侧壁上形成阻挡金属层，并在开口中形成钨层。