公开(公告)号：US20090179329A1

公开(公告)日：2009-07-16

申请号：US12345611

申请日：2008-12-29

申请人： Cheol Mo Jeong ,  Eun Soo Kim ,  Seung Hee Hong

发明人： Cheol Mo Jeong ,  Eun Soo Kim ,  Seung Hee Hong

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to semiconductor devices and a method of fabricating the same. According to a method of manufacturing semiconductor devices, there is first provided a semiconductor substrate in which a first pre-metal dielectric layer including trenches is formed. A diffusion barrier layer is formed on the entire surface including the trenches. A metal layer is formed on the diffusion barrier layer including the trenches, thereby gap-filling the trenches. A polish etching process is performed on the metal layer and the diffusion barrier layer so that the diffusion barrier layer and the metal layer remain within the trenches. An etching process of lowering a height of the metal layer is performed in order to increase a distance between metal lines. A capping layer is formed on the entire surface including exposed sidewalls of the first pre-metal dielectric layer. A second pre-metal dielectric layer is formed over the capping layer.

摘要翻译： 本发明涉及半导体器件及其制造方法。 根据制造半导体器件的方法，首先提供其中形成包括沟槽的第一预金属电介质层的半导体衬底。 在包括沟槽的整个表面上形成扩散阻挡层。 在包括沟槽的扩散阻挡层上形成金属层，从而间隙填充沟槽。 在金属层和扩散阻挡层上进行抛光蚀刻工艺，使得扩散阻挡层和金属层保留在沟槽内。 执行降低金属层的高度的蚀刻工艺，以增加金属线之间的距离。 在包括第一预金属介电层的暴露的侧壁的整个表面上形成覆盖层。 在覆盖层上方形成第二预金属介电层。

公开(公告)号：US07517793B2

公开(公告)日：2009-04-14

申请号：US11753543

申请日：2007-05-24

申请人： Seung Hee Hong ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Soo Kim

发明人： Seung Hee Hong ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Soo Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/28562 ,  H01L21/32131 ,  H01L21/76879 ,  H01L21/76882

摘要： A method of forming a metal wire in a semiconductor device includes performing a first etching process on an insulating layer formed on a semiconductor substrate to form a trench and an insulating layer pattern, the insulating layer pattern defining the trench. A barrier metal layer is formed over the insulating layer pattern and the trench. A second etching process is performed on the barrier metal layer to expose upper corners of the trench while leaving the trench substantially covered with the barrier metal layer. A metal layer is formed over the barrier metal layer in the trench. A heat treatment process is performed for reflowing the metal layer. The metal layer is planarized.

摘要翻译： 在半导体器件中形成金属线的方法包括对形成在半导体衬底上的绝缘层进行第一蚀刻工艺以形成沟槽和绝缘层图案，绝缘层图案限定沟槽。 在绝缘层图案和沟槽之上形成阻挡金属层。 在阻挡金属层上进行第二蚀刻工艺以暴露沟槽的上角，同时留下基本上被阻挡金属层覆盖的沟槽。 在沟槽中的阻挡金属层的上方形成有金属层。 进行用于回流金属层的热处理工艺。 金属层被平坦化。

公开(公告)号：US07504333B2

公开(公告)日：2009-03-17

申请号：US11614082

申请日：2006-12-21

申请人： Cheol Mo Jeong ,  Whee Won Cho ,  Eun Soo Kim ,  Seung Hee Hong

发明人： Cheol Mo Jeong ,  Whee Won Cho ,  Eun Soo Kim ,  Seung Hee Hong

IPC分类号： H01L21/20

CPC分类号： H01L21/76864 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/76846 ,  H01L21/76876

摘要： A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.

摘要翻译： 形成半导体器件的导电结构（例如位线）的方法包括在形成结构的半导体衬底上形成阻挡金属层。 在阻挡金属层上形成非晶氮化钛层。 在包含硼气体的气氛下，在非晶态氮化钛层上形成钨种子层。 在钨籽晶层上形成钨层，形成位线。

公开(公告)号：US08216932B2

公开(公告)日：2012-07-10

申请号：US12345611

申请日：2008-12-29

申请人： Cheol Mo Jeong ,  Eun Soo Kim ,  Seung Hee Hong

发明人： Cheol Mo Jeong ,  Eun Soo Kim ,  Seung Hee Hong

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to semiconductor devices and a method of fabricating the same. According to a method of manufacturing semiconductor devices, there is first provided a semiconductor substrate in which a first pre-metal dielectric layer including trenches is formed. A diffusion barrier layer is formed on the entire surface including the trenches. A metal layer is formed on the diffusion barrier layer including the trenches, thereby gap-filling the trenches. A polish etching process is performed on the metal layer and the diffusion barrier layer so that the diffusion barrier layer and the metal layer remain within the trenches. An etching process of lowering a height of the metal layer is performed in order to increase a distance between metal lines. A capping layer is formed on the entire surface including exposed sidewalls of the first pre-metal dielectric layer. A second pre-metal dielectric layer is formed over the capping layer.

摘要翻译： 本发明涉及半导体器件及其制造方法。 根据制造半导体器件的方法，首先提供其中形成包括沟槽的第一预金属电介质层的半导体衬底。 在包括沟槽的整个表面上形成扩散阻挡层。 在包括沟槽的扩散阻挡层上形成金属层，从而间隙填充沟槽。 在金属层和扩散阻挡层上进行抛光蚀刻工艺，使得扩散阻挡层和金属层保留在沟槽内。 执行降低金属层的高度的蚀刻工艺，以增加金属线之间的距离。 在包括第一预金属介电层的暴露的侧壁的整个表面上形成覆盖层。 在覆盖层上方形成第二预金属介电层。

公开(公告)号：US07601632B2

公开(公告)日：2009-10-13

申请号：US11646925

申请日：2006-12-27

申请人： Eun Soo Kim ,  Cheol Mo Jeong ,  Seung Hee Hong

发明人： Eun Soo Kim ,  Cheol Mo Jeong ,  Seung Hee Hong

IPC分类号： H01L21/00

CPC分类号： H01L21/76882 ,  H01L21/76838 ,  H01L21/76865 ,  H01L21/76879

摘要： A first conductive layer is formed over a substrate in which contact holes are formed in an interlayer insulating layer. The first conductive layer is melted by an annealing process, thus coating the lower sidewalls of the contact holes and partially filling the contact holes. A second conductive layer is deposited with a method having selectivity with respect to the same material as the first conductive layer, thus fully filling the contact holes. A metal line is formed on the second conductive layer. The contact holes are completely filled with a conductive material and the load of a CMP process can be alleviated. Accordingly, the electrical characteristics of a device can be improved, process reliability can be improved, and process repeatablity can be improved.

摘要翻译： 在层间绝缘层中形成有接触孔的基板上形成第一导电层。 第一导电层通过退火工艺熔化，从而涂覆接触孔的下侧壁并部分填充接触孔。 以与第一导电层相同的材料具有选择性的方法沉积第二导电层，从而完全填充接触孔。 金属线形成在第二导电层上。 接触孔完全充满导电材料，可以减轻CMP工艺的负荷。 因此，可以提高器件的电气特性，提高工艺可靠性，提高加工的可重复性。

公开(公告)号：US07557033B2

公开(公告)日：2009-07-07

申请号：US11647087

申请日：2006-12-27

申请人： Eun Soo Kim ,  Seung Hee Hong ,  Cheol Mo Jeong ,  Jung Geun Kim

发明人： Eun Soo Kim ,  Seung Hee Hong ,  Cheol Mo Jeong ,  Jung Geun Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/32139 ,  H01L21/76837

摘要： A method of forming a metal line of a semiconductor memory device includes the steps of forming plugs of a damascene structure in a first interlayer insulating layer over a semiconductor substrate, forming a barrier metal layer, a metal layer and an anti-reflection layer on the resulting surface, etching the anti-reflection layer, the metal layer, and the barrier metal layer according a specific pattern, and forming an insulating layer on sidewalls of the metal layer.

摘要翻译： 形成半导体存储器件的金属线的方法包括以下步骤：在半导体衬底上的第一层间绝缘层中形成镶嵌结构的插塞，在其上形成阻挡金属层，金属层和抗反射层 根据特定图案蚀刻抗反射层，金属层和阻挡金属层，并在金属层的侧壁上形成绝缘层。

公开(公告)号：US20080146023A1

公开(公告)日：2008-06-19

申请号：US11753543

申请日：2007-05-24

申请人： Seung Hee HONG ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Soo Kim

发明人： Seung Hee HONG ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Eun Soo Kim

IPC分类号： H01L21/44

CPC分类号： H01L21/28562 ,  H01L21/32131 ,  H01L21/76879 ,  H01L21/76882

摘要： A method of forming a metal wire in a semiconductor device includes performing a first etching process on an insulating layer formed on a semiconductor substrate to form a trench and an insulating layer pattern, the insulating layer pattern defining the trench. A barrier metal layer is formed over the insulating layer pattern and the trench. A second etching process is performed on the barrier metal layer to expose upper corners of the trench while leaving the trench substantially covered with the barrier metal layer. A metal layer is formed over the barrier metal layer in the trench. A heat treatment process is performed for reflowing the metal layer. The metal layer is planarized.

摘要翻译： 在半导体器件中形成金属线的方法包括对形成在半导体衬底上的绝缘层进行第一蚀刻工艺以形成沟槽和绝缘层图案，绝缘层图案限定沟槽。 在绝缘层图案和沟槽之上形成阻挡金属层。 在阻挡金属层上进行第二蚀刻工艺以暴露沟槽的上角，同时留下基本上被阻挡金属层覆盖的沟槽。 在沟槽中的阻挡金属层的上方形成有金属层。 进行用于回流金属层的热处理工艺。 金属层被平坦化。

公开(公告)号：US20080081453A1

公开(公告)日：2008-04-03

申请号：US11603752

申请日：2006-11-22

申请人： Jung Geun Kim ,  Cheol Mo Jeong ,  Eun Soo Kim ,  Seung Hee Hong

发明人： Jung Geun Kim ,  Cheol Mo Jeong ,  Eun Soo Kim ,  Seung Hee Hong

IPC分类号： H01L21/44

CPC分类号： H01L21/76831 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/7688

摘要： A method of forming a metal line of a semiconductor device includes the steps of forming an insulating layer and a glue layer on a semiconductor substrate, removing a portion of the glue layer and the insulating layer to form trenches, forming a metal layer over the semiconductor substrate including the trenches and the glue layer, and performing a polishing process until the insulating layer is exposed, thus forming a metal line.

摘要翻译： 形成半导体器件的金属线的方法包括以下步骤：在半导体衬底上形成绝缘层和胶层，去除一部分胶层和绝缘层以形成沟槽，在半导体上形成金属层 包括沟槽和胶层的衬底，并且进行抛光工艺直到绝缘层露出，从而形成金属线。

公开(公告)号：US20080003814A1

公开(公告)日：2008-01-03

申请号：US11647087

申请日：2006-12-27

申请人： Eun Soo Kim ,  Seung Hee Hong ,  Cheol Mo Jeong ,  Jung Geun Kim

发明人： Eun Soo Kim ,  Seung Hee Hong ,  Cheol Mo Jeong ,  Jung Geun Kim

IPC分类号： H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/32139 ,  H01L21/76837

摘要： A method of forming a metal line of a semiconductor memory device includes the steps of forming plugs of a damascene structure in a first interlayer insulating layer over a semiconductor substrate, forming a barrier metal layer, a metal layer and an anti-reflection layer on the resulting surface, etching the anti-reflection layer, the metal layer, and the barrier metal layer according a specific pattern, and forming an insulating layer on sidewalls of the metal layer.

摘要翻译： 形成半导体存储器件的金属线的方法包括以下步骤：在半导体衬底上的第一层间绝缘层中形成镶嵌结构的插塞，在其上形成阻挡金属层，金属层和抗反射层 根据特定图案蚀刻抗反射层，金属层和阻挡金属层，并在金属层的侧壁上形成绝缘层。

公开(公告)号：US20080003796A1

公开(公告)日：2008-01-03

申请号：US11614082

申请日：2006-12-21

申请人： Cheol Mo JEONG ,  Whee Won Cho ,  Eun Soo Kim ,  Seung Hee Hong

发明人： Cheol Mo JEONG ,  Whee Won Cho ,  Eun Soo Kim ,  Seung Hee Hong

IPC分类号： H01L21/44

CPC分类号： H01L21/76864 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/76846 ,  H01L21/76876

摘要： A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.

摘要翻译： 形成半导体器件的导电结构（例如位线）的方法包括在形成结构的半导体衬底上形成阻挡金属层。 在阻挡金属层上形成非晶氮化钛层。 在包含硼气体的气氛下，在非晶态氮化钛层上形成钨种子层。 在钨籽晶层上形成钨层，形成位线。