公开(公告)号：US06370053B2

公开(公告)日：2002-04-09

申请号：US09761880

申请日：2001-01-17

Applicant: Nai-Shung Chang ,  Chia-Hsin Chen

Inventor： Nai-Shung Chang ,  Chia-Hsin Chen

IPC: G11C502

CPC classification number: H05K1/0246 ,  G11C8/06 ,  G11C8/12 ,  H05K1/0262 ,  H05K1/14 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10022 ,  H05K2201/10159

Abstract: A memory address driver circuit with memory module slots on a computer main board that can be divided into two groups. One group of memory module slots includes the slots whose trace line to a control chipset is smaller than 2500 mils or closest to the control chipset. The other group of memory module slots includes all the remaining slots. The control chipset includes two memory control circuits. The memory control circuit for supporting DDR DRAM is connected to the address leads of the memory module slot closest to the control chipset. However, no terminal resistors are connected to any address leads of the memory module slot. Hence, engineers may have to design one set of terminal resistors only. In addition, the memory control circuit uses one-cycle access command timing to boost system performance.

Abstract translation: 一个内存地址驱动电路，其内存模块插槽位于计算机主板上，可分为两组。 一组存储器模块插槽包括其控制芯片组的跟踪线小于2500密耳或最接近控制芯片组的插槽。 另一组内存模块插槽包括所有剩余的插槽。 控制芯片组包括两个存储器控制电路。 用于支持DDR DRAM的存储器控​​制电路连接到最靠近控制芯片组的存储器模块插槽的地址引线。 但是，没有端子电阻连接到内存模块插槽的任何地址引线。 因此，工程师可能只需要设计一组端子电阻。 此外，存储器控制电路使用一周期访问命令定时来提高系统性能。

公开(公告)号：US20110289260A1

公开(公告)日：2011-11-24

申请号：US13014735

申请日：2011-01-27

Applicant: Chi-Lung Wang ,  Chia-Hsin Chen ,  Chien-Cheng Lin

Inventor： Chi-Lung Wang ,  Chia-Hsin Chen ,  Chien-Cheng Lin

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F12/10 ,  G06F2212/7201

Abstract: A method for performing block management is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: adjusting a dynamic threshold according to at least one condition; and comparing a valid/invalid page count of a specific block of the plurality of blocks with the dynamic threshold to determine whether to erase the specific block. An associated memory device and a controller thereof are also provided, where the memory device includes the Flash memory and the controller. In particular, the controller includes a read only memory (ROM) arranged to store a program code, and further includes a microprocessor arranged to execute the program code to control access to the Flash memory and manage the plurality of blocks, where under control of the microprocessor, the controller operates according to the method.

Abstract translation: 提供了一种执行块管理的方法。 该方法应用于闪速存储器的控制器，其中闪速存储器包括多个块。 该方法包括：根据至少一个条件调整动态阈值; 以及将所述多个块中的特定块的有效/无效页面计数与所述动态阈值进行比较，以确定是否擦除所述特定块。 还提供了一种相关联的存储器件及其控制器，其中存储器件包括闪存和控制器。 特别地，控制器包括被布置为存储程序代码的只读存储器（ROM），并且还包括微处理器，其被布置为执行程序代码以控制对闪存的访问并管理多个块，其中在 微处理器，控制器根据方法进行操作。

公开(公告)号：US07962683B2

公开(公告)日：2011-06-14

申请号：US12014991

申请日：2008-01-16

Applicant: Chia-Hsin Chen ,  Chun-Kun Lee

Inventor： Chia-Hsin Chen ,  Chun-Kun Lee

IPC: G06F12/00

CPC classification number: G06F12/0804 ,  G06F2212/2022

Abstract: A method for operating a flash memory is provided. The flash memory comprises a controller, a cache, and a plurality of blocks. By using a cache to preload data from the host, the buffer of the controller can be smaller than the capacity of a single block or omitted entirely. Smooth data transmission is still maintained.

Abstract translation: 提供了一种用于操作闪速存储器的方法。 闪存包括控制器，高速缓存和多个块。 通过使用缓存从主机预加载数据，控制器的缓冲区可以小于单个块的容量或完全省略。 平稳的数据传输仍然保持不变。

公开(公告)号：US20100169555A1

公开(公告)日：2010-07-01

申请号：US12632668

申请日：2009-12-07

Applicant: Chien-Ping Chung ,  Chia-Hsin Chen ,  Ming-Che Liu

Inventor： Chien-Ping Chung ,  Chia-Hsin Chen ,  Ming-Che Liu

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7206

Abstract: A method of writing data into flash memory based on OS file system is provided. The method includes steps of: obtaining a data start position of a data area in a first partition of a flash memory; converting the data start position into a first block number and a first page number; calculating an offset and adding the offset to the first page number to be an updated first page number when the first page number is not an integer; and, setting the first block number and the updated first page number as a new data start position of the data area and writing a first data according to the new data start position.

Abstract translation: 提供了一种基于OS文件系统将数据写入闪存的方法。 该方法包括以下步骤：获取快闪存储器的第一分区中的数据区的数据开始位置; 将数据开始位置转换成第一块号和第一页号; 当第一页数不是整数时，计算偏移量并将偏移量添加到第一页数作为更新的第一页数; 并且将第一块号和更新的第一页号设置为数据区的新数据开始位置，并根据新数据开始位置写入第一数据。

公开(公告)号：US20090210758A1

公开(公告)日：2009-08-20

申请号：US12241307

申请日：2008-09-30

Applicant: Chun-Hao Huang ,  Chia-Hsin Chen ,  Ming-Che Liu

Inventor： Chun-Hao Huang ,  Chia-Hsin Chen ,  Ming-Che Liu

IPC: G11C29/00

CPC classification number: G06F11/1068

Abstract: A method for a flash memory storage device to use a copy back command includes the following steps. The method includes the step of copying a data in a first block of a flash memory to a buffer outside the flash memory, checking if the data in the buffer is correct, and copying the data in the first block of the flash memory to a second block in the flash memory when the data in the buffer is correct.

Abstract translation: 闪存存储装置使用复制命令的方法包括以下步骤。 该方法包括将闪速存储器的第一块中的数据复制到闪速存储器外部的缓冲器的步骤，检查缓冲器中的数据是否正确，以及将闪存的第一块中的数据复制到第二块 当缓冲区中的数据正确时，在闪存中阻塞。

公开(公告)号：US20090144488A1

公开(公告)日：2009-06-04

申请号：US12050205

申请日：2008-03-18

Applicant: Chia-Hsin Chen

Inventor： Chia-Hsin Chen

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: The invention provides a method for handling data updating of a flash memory. In one embodiment, the flash memory comprises a mother block comprising a plurality of updated pages to be updated. First, a spare block, recording no data, is popped as a file allocation table (FAT) block corresponding to the mother block. Data for updating the updated pages of the mother block is then written to a plurality of replacing pages of the FAT block. Finally, a plurality of mapping relationships between the replacing pages and the updated pages are recorded in a page mapping table stored in the FAT block.

Abstract translation: 本发明提供了一种处理闪速存储器的数据更新的方法。 在一个实施例中，闪速存储器包括母块，其包括要更新的多个更新的页面。 首先，将不记录数据的备用块作为与母块对应的文件分配表（FAT）块而弹出。 然后将用于更新母块的更新页面的数据写入FAT块的多个替换页面。 最后，替换页面和更新页面之间的多个映射关系被记录在存储在FAT块中的页面映射表中。

公开(公告)号：US20070146510A1

公开(公告)日：2007-06-28

申请号：US11379398

申请日：2006-04-20

Applicant: Ching-Hsiu Lin ,  Chia-Hsin Chen ,  Lien-Wei Lee

Inventor： Ching-Hsiu Lin ,  Chia-Hsin Chen ,  Lien-Wei Lee

IPC: H04N5/202

CPC classification number: H04N5/14 ,  G09G3/3611 ,  G09G3/3614 ,  G09G2320/0233 ,  G09G2320/0285 ,  G09G2320/0693 ,  H04N5/202 ,  H04N5/57 ,  H04N9/69 ,  H04N17/04 ,  H04N21/4318

Abstract: An image processing module substantially matches the representation of a display with the expectation of image data. The image processing module comprises a storage unit, a control unit, and an image processing unit. The storage unit stores calibration information with calibration values each corresponding to a physical area on the display. The control unit receives timing data and mode data to accordingly direct the storage unit to output corresponding calibration value. An image processing unit is controlled by the control unit to calibrate the image data according to the corresponding calibration value and output calibrated image data.

Abstract translation: 图像处理模块基本上使显示器的表示与图像数据的期望相匹配。 图像处理模块包括存储单元，控制单元和图像处理单元。 存储单元存储具有与显示器上的物理区域对应的校准值的校准信息。 控制单元接收定时数据和模式数据，以相应地指示存储单元输出相应的校准值。 图像处理单元由控制单元控制，以根据相应的校准值校准图像数据并输出经校准的图像数据。

公开(公告)号：US20070030281A1

公开(公告)日：2007-02-08

申请号：US11431543

申请日：2006-05-11

Applicant: Chia-Hsin Chen

Inventor： Chia-Hsin Chen

IPC: G09G5/39

CPC classification number: G09G5/363

Abstract: The present invention provides an IC chip of a serial memory script controller, comprising: an interface transforming unit, an I/O buffer and data path control unit, a script decoder, an ALU and an event control unit. The interface transforming unit codes and decodes a communication protocol of a serial interface; the I/O buffer and data path control unit is electrically connected to the interface transforming unit, stores the input and output data of the interface transforming unit; and selects and controls the data path; the script decoder is electrically connected to the input/output buffer and data path control unit, and decode a program code stored in the input/output buffer and data path control unit, and then a corresponding control signal is transformed; the ALU is electrically connected to the input/output buffer and data path control unit and the script decoder, and executes an instruction operation in accordance with data of the input/output buffer and data path control unit and the script decoder; and the event control unit is electrically connected to the interface transforming unit, the input/output buffer and data path control unit, and the script decoder, and receives an event, wherein the interface transforming unit, the input/output buffer and data path control unit, and the script decoder execute processing and operation in accordance with the event. The serial memory script controller built in an IC chip to simplify the architecture inside the IC to achieve the advantages of the minification, thinning, increasing the performance, and decreasing the power consumption.

Abstract translation: 本发明提供一种串行存储器脚本控制器的IC芯片，包括：接口变换单元，I / O缓冲器和数据路径控制单元，脚本解码器，ALU和事件控制单元。 接口变换单元对串行接口的通信协议进行编码和解码; I / O缓冲器和数据路径控制单元电连接到接口变换单元，存储接口变换单元的输入和输出数据; 并选择并控制数据路径; 脚本解码器电连接到输入/输出缓冲器和数据路径控制单元，并对存储在输入/输出缓冲器和数据路径控制单元中的程序代码进行解码，然后对相应的控制信号进行变换; ALU电连接到输入/输出缓冲器和数据路径控制单元和脚本解码器，并且根据输入/输出缓冲器和数据路径控制单元和脚本解码器的数据执行指令操作; 并且事件控制单元电连接到接口变换单元，输入/输出缓冲器和数据路径控制单元以及脚本解码器，并且接收事件，其中接口变换单元，输入/输出缓冲器和数据路径控制 单元，脚本解码器根据事件执行处理和操作。 串行内存脚本控制器内置IC芯片，简化了IC内部的架构，实现了细化，减薄，增加性能和降低功耗的优点。

公开(公告)号：US20050088451A1

公开(公告)日：2005-04-28

申请号：US10692683

申请日：2003-10-27

Applicant: Chia-Hsin Chen

Inventor： Chia-Hsin Chen

IPC: G09G5/36 ,  G09G5/391

CPC classification number: G09G5/391 ,  G09G2340/145

Abstract: A method for an image reducing processing circuit includes the memory architecture of two FIFO units. The method includes the following steps of: providing an input processing unit receiving original image data and delivering the image data; providing a horizontal direction image processing unit receiving the image data from the input processing unit; providing a first step FIFO unit receiving the image data from the horizontal direction image processing unit to read and write the image data on the same access frequency; providing a vertical direction image processing unit receiving the image data from the first step FIFO unit; providing a second step FIFO unit receiving the image data from the vertical direction image processing unit and implementing the readout/writing of the image data on two access frequency, and providing an output processing unit receiving the image data from the second step FIFO unit and outputting reduced image.

Abstract translation: 一种图像缩小处理电路的方法包括两个FIFO单元的存储架构。 该方法包括以下步骤：提供接收原始图像数据并传送图像数据的输入处理单元; 提供从所述输入处理单元接收所述图像数据的水平方向图像处理单元; 提供从水平方向图像处理单元接收图像数据以在相同的存取频率上读取和写入图像数据的第一级FIFO单元; 提供从所述第一步骤FIFO单元接收所述图像数据的垂直方向图像处理单元; 提供从垂直方向图像处理单元接收图像数据并实现在两个存取频率上的图像数据的读出/写入的第二步骤FIFO单元，并且提供从第二步FIFO单元接收图像数据的输出处理单元并输出 缩小图像。

公开(公告)号：US08843663B2

公开(公告)日：2014-09-23

申请号：US13662566

申请日：2012-10-29

Applicant: Ming-Hui Chiu ,  Chia-Hsin Chen

Inventor： Ming-Hui Chiu ,  Chia-Hsin Chen

IPC: G06F3/06 ,  G06F3/00 ,  G06F13/12

CPC classification number: G06F3/00 ,  G06F3/038 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0674

Abstract: A data transmission device and a command merging method for data transmission are provided. The data transmission device includes a command register and a command merging unit. The command register receives and temporary storages a plurality of original commands, wherein the original commands include a plurality of memory blocks. When the command merging unit judges these memory blocks of the original commands to be a continuous memory block, the command merging unit merges the original commands into a merging command, and transmits the merging command to a peripheral device. Thus, the multiple commands send by the host can be analyzed and merged by the data transmission device to decrease a number of the commands to be proceed by the peripheral device, so as to speed up a command processing time of the peripheral device efficiently.

Abstract translation: 提供了一种用于数据传输的数据传输设备和命令合并方法。 数据传输装置包括命令寄存器和命令合并单元。 命令寄存器接收和临时存储多个原始命令，其中原始命令包括多个存储器块。 当命令合并单元将原始命令的这些存储块判断为连续存储块时，命令合并单元将原始命令合并成合并命令，并将合并命令发送到外围设备。 因此，由主机发送的多个命令可以由数据传输装置进行分析和合并，以减少由外围设备进行的命令的数量，以便有效地加速外围设备的命令处理时间。