公开(公告)号：US20080059927A1

公开(公告)日：2008-03-06

申请号：US11832465

申请日：2007-08-01

申请人： Burkhard Ludwig ,  Uwe Mueller

发明人： Burkhard Ludwig ,  Uwe Mueller

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method and a device can be used for checking the layout of an electronic circuit of a semiconductor component. For example, the method includes an automatic classification of cells in at least one layout into a cell database, and an automatic layout checker comparing the cell database to a layout to be checked.

摘要翻译： 可以使用方法和装置来检查半导体部件的电子电路的布局。 例如，该方法包括将至少一个布局中的单元格自动分类为单元数据库，以及将单元数据库与要检查的布局进行比较的自动布局检查器。

公开(公告)号：US06913983B1

公开(公告)日：2005-07-05

申请号：US09462994

申请日：1998-05-11

申请人： Udo Schwalke ,  Burkhard Ludwig

发明人： Udo Schwalke ,  Burkhard Ludwig

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L21/20 ,  H01L29/80

CPC分类号： H01L23/485 ,  H01L21/76819 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A doped region is provided on a substrate. A plane with conductive useful structures and a conductive filler structure is arranged at the surface of the substrate. The conductive filler structure is conductively connected to the doped region. In this way, charging of the conductive filler structure, which is provided for improving the planarity of the circuit arrangement and has no circuit-oriented function, is avoided.

摘要翻译： 掺杂区域设置在基板上。 具有导电有用结构和导电填料结构的平面布置在衬底的表面。 导电填料结构与掺杂区导电连接。 以这种方式，避免了用于提高电路布置的平面性并且不具有电路定向功能的导电填料结构的充电。

公开(公告)号：US20060190850A1

公开(公告)日：2006-08-24

申请号：US11348549

申请日：2006-02-07

申请人： Roderick Kohle ,  Burkhard Ludwig ,  Michael Heissmeier ,  Armin Semmler ,  Dirk Meyer ,  Christoph Nolscher ,  Jorg Thiele

发明人： Roderick Kohle ,  Burkhard Ludwig ,  Michael Heissmeier ,  Armin Semmler ,  Dirk Meyer ,  Christoph Nolscher ,  Jorg Thiele

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A method for optimizing the geometry of structural elements of a circuit pattern involves providing an overall circuit pattern of the circuit design and a plurality of basic patterns. Subsequently, the circuit pattern of the circuit design is iteratively decomposed into corresponding basic patterns in order to classify those parts of the circuit pattern of the plurality of structural elements wherein there exists a match with the basic pattern. Subsequently, further basic patterns are determined for those parts of the circuit pattern which were not previously classified. After applying a specification for optimizing the geometry of the structural elements, the optimized basic patterns are inserted into the circuit design thus achieving an improvement of the optical imaging properties.

摘要翻译： 用于优化电路图案的结构元件的几何形状的方法包括提供电路设计和多个基本图案的总体电路图案。 随后，将电路设计的电路图案迭代地分解为对应的基本图案，以便对存在与基本图案相匹配的多个结构元件的电路图案的那些部分进行分类。 随后，对于以前未分类的电路图形的那些部分，确定了另外的基本模式。 在应用用于优化结构元件的几何形状的规范之后，将优化的基本图案插入到电路设计中，从而实现光学成像特性的改进。

公开(公告)号：US06981241B2

公开(公告)日：2005-12-27

申请号：US10455764

申请日：2003-06-05

申请人： Burkhard Ludwig ,  Molela Moukara

发明人： Burkhard Ludwig ,  Molela Moukara

IPC分类号： G03F1/00 ,  G06F17/50

CPC分类号： G03F1/30

摘要： In order to eliminate phase conflicts in alternating phase masks, the layout is modified after the phase conflicts have been localized. During the modification, degenerate critical structures, which fall below a minimum width and require phase-shifting regions for their adequate imaging, are widened, so that the phase-shifting regions directly adjoining the degenerate critical structures disappear. Moreover, interaction regions between phase-shifting regions can be eliminated by trimming masks, intermediate phases or shifting associated critical structures.

摘要翻译： 为了消除交替相位掩模中的相位冲突，在本地化相位冲突之后，修改布局。 在修改期间，落入低于最小宽度并且需要用于其适当成像的相移区域的退化临界结构被加宽，使得与退化关键结构直接相邻的相移区域消失。 此外，相移区域之间的相互作用区域可以通过修剪掩模，中间相位或移相关联结构来消除。

公开(公告)号：US20050095512A1

公开(公告)日：2005-05-05

申请号：US10928759

申请日：2004-08-27

申请人： Molela Moukara ,  Burkhard Ludwig ,  Jorg Thiele ,  Marco Ahrens ,  Roderick Kohle ,  Rainer Pforr ,  Nicolo Morgana

发明人： Molela Moukara ,  Burkhard Ludwig ,  Jorg Thiele ,  Marco Ahrens ,  Roderick Kohle ,  Rainer Pforr ,  Nicolo Morgana

IPC分类号： G03C5/00 ,  G03F1/00 ,  G03F7/20 ,  G03F9/00

CPC分类号： G03F7/70441 ,  G03F1/30 ,  G03F1/36 ,  G03F7/70466

摘要： A lithography mask has an angled structure element (O) formed by a first opaque segment (O1) and by a second opaque segment (O2). The structure element has at least one reflex angle (α). The angled structure element (O) includes at least one convex section (A) facing the reflex angle (α). At least one transparent structure (T) adjacent to the angled structure element (O) is provided at the convex section (A) of the angled structure element (O). The transparent structure (T) is formed in separated fashion at the convex section (A) of the angled structure element (O) and thus comprises two distinguishable transparent segments (T1, T2) formed at least in sections essentially axially symmetrically with respect to the angle bisector (WH) of the reflex angle.

摘要翻译： 光刻掩模具有由第一不透明部分（O 1）和第二不透明部分（O 2）形成的成角度的结构元件（O）。 结构元件具有至少一个反射角（α）。 倾斜结构元件（O）包括面向反射角（α）的至少一个凸部（A）。 与成角度的结构元件（O）相邻的至少一个透明结构（T）设置在倾斜结构元件（O）的凸部（A）处。 透明结构（T）以分开的方式形成在成角度的结构元件（O）的凸部（A）处，因此包括两个可区分的透明段（T 1，T 2），其至少形成在主要轴向对称的部分 到角度平分线（WH）的反射角度。

公开(公告)号：US06730463B2

公开(公告)日：2004-05-04

申请号：US10126371

申请日：2002-04-19

申请人： Michael Heissmeier ,  Markus Hofsäss ,  Burkhard Ludwig ,  Molela Moukara ,  Christoph Nölscher

发明人： Michael Heissmeier ,  Markus Hofsäss ,  Burkhard Ludwig ,  Molela Moukara ,  Christoph Nölscher

IPC分类号： G03C500

CPC分类号： G03F1/30

摘要： A photoresist layer on a substrate wafer is exposed in first sections with a first exposure radiation and in second sections with a second exposure radiation that is phase-shifted by 180°. The first and second sections adjoin one another in boundary regions in which the photoresist layer is artificially not sufficiently exposed. Where a distance between these boundary regions is smaller than a photolithographically critical, least distance, the photoresist layer is exposed, at a first boundary region, with a third exposure radiation and at a second boundary region with a fourth exposure radiation phase-shifted by 180°. A trim mask provided for the process has a first translucent region and a second translucent region. The first light-transparent region and the second light-transparent region are fashioned such that the light passing through the first light-transparent region and the light passing through the second light-transparent region has a phase displacement of 180°.

摘要翻译： 衬底晶片上的光致抗蚀剂层在具有第一曝光辐射的第一部分中暴露，并且在第二部分中具有相移180°的第二曝光辐射。 第一和第二部分在其中光致抗蚀剂层人为地不充分暴露的边界区域彼此相邻。 在这些边界区域之间的距离小于光刻临界的最小距离的情况下，光致抗蚀剂层在第一边界区域处以第三曝光辐射暴露，并且在第二边界区域处以第四曝光辐射相位偏移180° °。 为该工艺提供的修剪掩模具有第一半透明区域和第二半透明区域。 第一透光区域和第二透光区域被形成为使得穿过第一透光区域的光和穿过第二透光区域的光线具有180°的相位偏移。

公开(公告)号：US06543045B2

公开(公告)日：2003-04-01

申请号：US09978396

申请日：2001-10-16

申请人： Burkhard Ludwig ,  Molela Moukara

发明人： Burkhard Ludwig ,  Molela Moukara

IPC分类号： G06F1750

CPC分类号： G03F1/30

摘要： A method for eliminating phase conflicts that occur in the layout of a phase mask in a localized and automated manner. The method includes a first step in which a set of phase conflicts is completely determined exclusively by using the technical requirements of the design. The first step is an optimum starting point for the following second step for automatically handling and eliminating such conflicts.

公开(公告)号：US06493865B2

公开(公告)日：2002-12-10

申请号：US09829870

申请日：2001-04-10

申请人： Werner Fischer ,  Burkhard Ludwig ,  Dirk Meyer ,  Jörg Thiele

发明人： Werner Fischer ,  Burkhard Ludwig ,  Dirk Meyer ,  Jörg Thiele

IPC分类号： G06F1750

CPC分类号： G03F1/70

摘要： Masks are produced for the fabrication of semiconductor structures based on layout data that has information for defining a mask layout with individual geometric structure elements. Layout data generated previously for a mask layout is checked to see whether geometric design requirements are satisfied. In the event of a violation of design requirements, the corresponding error locations in the mask layout are located. Further layout data are then generated, which contain information for defining correction figures to correct the respective error locations. The further layout data are linked with the layout data, so that the layout data are modified. This permits automated modification of the layout data and their technology-dependent optimization.