Method for classifying errors in the layout of a semiconductor circuit
    1.
    发明授权
    Method for classifying errors in the layout of a semiconductor circuit 有权
    对半导体电路布局中的误差进行分类的方法

    公开(公告)号:US07716613B2

    公开(公告)日:2010-05-11

    申请号:US11712635

    申请日:2007-03-01

    CPC classification number: G06F17/5081

    Abstract: A method for classifying errors in the layout of a semiconductor circuit includes examining the layout of the semiconductor circuit for infringement of predetermined design rules in order to establish errors. For each error, the error is marked in the layout, and information about the error and the layout of the semiconductor circuit in an area surrounding the error is extracted. The extracted information is compared with prestored information within a multiplicity of classes, and the error is assigned to the respective class on the basis of the compared information.

    Abstract translation: 用于对半导体电路的布局中的误差进行分类的方法包括:检查半导体电路的布局,以便违反预定的设计规则以建立错误。 对于每个错误,在布局中标记错误,并提取关于错误周围区域中的半导体电路的错误和布局的信息。 将所提取的信息与多个类中的预存信息进行比较,并且基于所比较的信息将错误分配给相应的类。

    Quality printing method, printing machine, and corresponding printing substance
    2.
    发明授权
    Quality printing method, printing machine, and corresponding printing substance 有权
    优质印刷方式,印刷机及相应的印刷品

    公开(公告)号:US07154522B2

    公开(公告)日:2006-12-26

    申请号:US10506591

    申请日:2003-02-19

    CPC classification number: C09D11/03 B41J2/0057 B41J2/442 B41M1/00 B41M5/025

    Abstract: A printing process for the transfer of printing substance (2) from an ink carrier (1) to an imprinting material (6), in which, with the help of an energy-emitting apparatus, which, during a process period, emits energy in the form of electromagnetic waves (3), and the printing substance (2) undergoes a change in volume and/or position, wherein, with the help of absorption bodies (4), energy is transferred from the electromagnetic waves (3) into the printing substance (2). The invention also includes an apparatus for practicing the process of the invention and a printing substance containing absorption bodies.

    Abstract translation: 一种用于将印刷物质(2)从油墨载体(1)转移到压印材料(6)的印刷方法,其中借助于能量发射装置,其在处理期间发射能量 电磁波(3)的形式和打印物质(2)经历体积和/或位置的变化,其中借助于吸收体(4),能量从电磁波(3)转移到 印刷物质(2)。 本发明还包括用于实施本发明方法的装置和含有吸收体的印刷物质。

    Accelerator pedal module
    3.
    发明授权
    Accelerator pedal module 失效
    加速踏板模块

    公开(公告)号:US06834564B2

    公开(公告)日:2004-12-28

    申请号:US10019017

    申请日:2002-07-26

    CPC classification number: G05G1/30 B60K26/02 G05G5/03 Y10T74/20534 Y10T74/2054

    Abstract: An accelerator module actuated by the driver's foot for controlling the output of a driving engine or motor of a motor vehicle employs a friction element for generating a friction hysteresis for the purpose of achieving a comfortable driving feel. Support of the pedal lever is completely independent of the generation of the friction hysteresis, resulting in a particularly favorable, especially stable, and play-free support of the pedal lever, and the brake insert for generating the friction hysteresis is particularly easy to manufacture.

    Abstract translation: 用于控制机动车辆的驱动发动机或马达的输出的由驾驶员脚驱动的加速器模块采用用于产生摩擦滞后的摩擦元件,以实现舒适的驾驶感觉。 踏板杆的支撑完全不依赖于摩擦滞后的产生,导致踏板杆特别有利的,特别稳定的和无游隙的支撑,并且用于产生摩擦滞后的制动器插件特别容易制造。

    Phosphating process
    4.
    发明授权
    Phosphating process 失效
    磷化工艺

    公开(公告)号:US5135583A

    公开(公告)日:1992-08-04

    申请号:US749191

    申请日:1991-08-23

    CPC classification number: C23C22/362 C23C22/86

    Abstract: For phosphating metal surfaces which consist at least in part of aluminum, by means of phosphating solutions which contain zinc, phosphate and fluoride, any titanium which has entered the phosphating solution and would disturb the formation of the layer is precipitated by an addition of SiO-containing compounds and after the precipitate has been removed, the content of free fluoride is readjusted to the required concentration. Particularly suitable compounds which contain SiO, consist of alkali metasilicate, alkali orthosilicate and/or alkali disilicate, preferably used in an amount of 0.05 to 1 g/l of the phosphating solution, or of silica, which is preferably used in an amount of 0.5 to 10 g per liter of the phosphating solution (calc. as Si).

    Abstract translation: 对于至少部分由铝组成的磷化金属表面,通过含有锌,磷酸盐和氟化物的磷化溶液,已经进入磷化溶液并且将扰乱层的形成的任何钛通过加入SiO- 在除去沉淀物之后,将游离氟化物的含量重新调节至所需浓度。 含有SiO的特别合适的化合物由偏硅酸碱,原硅酸碱和/或碱二硅酸盐组成,优选以0.05至1g / l的磷酸盐溶液或二氧化硅的量使用,其优选以0.5的量使用 至10g每升磷酸盐溶液(计算为Si)。

    METHOD FOR INFORMATION RETRIEVAL IN A COMMUNICATION NETWORK
    5.
    发明申请
    METHOD FOR INFORMATION RETRIEVAL IN A COMMUNICATION NETWORK 审中-公开
    通信网络信息检索方法

    公开(公告)号:US20110139867A1

    公开(公告)日:2011-06-16

    申请号:US12964828

    申请日:2010-12-10

    Applicant: Dirk Meyer

    Inventor: Dirk Meyer

    CPC classification number: G06F16/9554

    Abstract: A method for information retrieval in a communication network includes step 1) of transmitting a reference information from a mobile source device to a network instance. The reference information includes at least one of an image of a barcode from an accessible media and a related information that is derived from the barcode. The source device includes a Public Land Mobile Network interface and the reference information is transmitted via the Public Land Mobile Network interface. A second step 2) includes transmitting a target information, including information related to a selected target device, to the network instance, the target information being transmitted via the Public Land Mobile Network interface. A third step 3) includes transmitting a usable information from the network instance to the target device, the usable information being related to the reference information and including a media content that is used by the target device at a predetermined time. Step 1) is completed before step 2) begins the step 2) is completed before step 3) begins.

    Abstract translation: 一种用于在通信网络中进行信息检索的方法包括将参考信息从移动源设备发送到网络实例的步骤1)。 参考信息包括来自可访问媒体的条形码的图像和从条形码导出的相关信息中的至少一个。 源设备包括公共陆地移动网络接口,并且参考信息经由公共陆地移动网络接口传送。 第二步骤2)包括将包括与所选择的目标设备相关的信息的目标信息发送到网络实例,目标信息通过公共陆地移动网络接口发送。 第三步骤3)包括从网络实例向目标设备发送可用信息,可用信息与参考信息相关,并且包括目标设备在预定时间使用的媒体内容。 步骤1)在步骤2之前完成,开始步骤2)在步骤3开始之前完成。

    Method for optimizing the geometry of structural elements of a circuit design pattern and method for producing a photomask
    6.
    发明申请
    Method for optimizing the geometry of structural elements of a circuit design pattern and method for producing a photomask 审中-公开
    用于优化电路设计图案的结构元件的几何形状的方法和用于制造光掩模的方法

    公开(公告)号:US20060190850A1

    公开(公告)日:2006-08-24

    申请号:US11348549

    申请日:2006-02-07

    CPC classification number: G03F1/36

    Abstract: A method for optimizing the geometry of structural elements of a circuit pattern involves providing an overall circuit pattern of the circuit design and a plurality of basic patterns. Subsequently, the circuit pattern of the circuit design is iteratively decomposed into corresponding basic patterns in order to classify those parts of the circuit pattern of the plurality of structural elements wherein there exists a match with the basic pattern. Subsequently, further basic patterns are determined for those parts of the circuit pattern which were not previously classified. After applying a specification for optimizing the geometry of the structural elements, the optimized basic patterns are inserted into the circuit design thus achieving an improvement of the optical imaging properties.

    Abstract translation: 用于优化电路图案的结构元件的几何形状的方法包括提供电路设计和多个基本图案的总体电路图案。 随后,将电路设计的电路图案迭代地分解为对应的基本图案,以便对存在与基本图案相匹配的多个结构元件的电路图案的那些部分进行分类。 随后,对于以前未分类的电路图形的那些部分,确定了另外的基本模式。 在应用用于优化结构元件的几何形状的规范之后,将优化的基本图案插入到电路设计中,从而实现光学成像特性的改进。

    Method for correcting layout errors
    7.
    发明申请
    Method for correcting layout errors 有权
    校正布局错误的方法

    公开(公告)号:US20060053400A1

    公开(公告)日:2006-03-09

    申请号:US11191167

    申请日:2005-07-27

    CPC classification number: G06F17/5081

    Abstract: A method for correcting layout errors of a layout, for example layout errors of a layout of an electronic circuit, is disclosed. In order to be able to correct such layout errors with the least possible complexity, the layout (10) is examined for the presence of layout errors (20, 30) with the aid of predetermined design rules, identical layout errors (20, 30) are combined in a respective error class, and all layout errors (30) of an error class that are still present are automatically corrected without further checking in an identical manner as soon as the correction of a layout error (20) of the respective error class that is used as an error representative has been performed.

    Abstract translation: 公开了一种用于校正布局的布局错误的方法,例如电子电路布局的布局错误。 为了能够以尽可能低的复杂度来校正这种布局错误,借助于预定的设计规则,检查布局(10)是否存在布局错误(20,30),相同的布局错误(20,30) 被组合在相应的错误类别中,并且一旦校正了相应错误等级的布局错误(20),则自动校正所有仍然存在的错误类的所有布局错误(30),而不进行相同的检查。 已经被用作错误代表。

    Method of producing masks for fabricating semiconductor structures

    公开(公告)号:US06493865B2

    公开(公告)日:2002-12-10

    申请号:US09829870

    申请日:2001-04-10

    CPC classification number: G03F1/70

    Abstract: Masks are produced for the fabrication of semiconductor structures based on layout data that has information for defining a mask layout with individual geometric structure elements. Layout data generated previously for a mask layout is checked to see whether geometric design requirements are satisfied. In the event of a violation of design requirements, the corresponding error locations in the mask layout are located. Further layout data are then generated, which contain information for defining correction figures to correct the respective error locations. The further layout data are linked with the layout data, so that the layout data are modified. This permits automated modification of the layout data and their technology-dependent optimization.

    Method and system for performing local geometrical operation on a hierarchical layout of a semiconductor device
    9.
    发明申请
    Method and system for performing local geometrical operation on a hierarchical layout of a semiconductor device 审中-公开
    用于在半导体器件的分层布局上执行局部几何运算的方法和系统

    公开(公告)号:US20070011637A1

    公开(公告)日:2007-01-11

    申请号:US11448169

    申请日:2006-06-06

    CPC classification number: G06F17/5081

    Abstract: At least one cell pair graph is generated for cells of the layout. A partial inverse layout tree is determined from the cell pair graph. For the partial inverse layout tree, only branches of the complete inverse layout tree are considered that describe an interaction between shapes of different cells. A data set is generated from the partial inverse layout tree and the data set is saved, for example, by using the partial inverse layout tree.

    Abstract translation: 为布局的单元格生成至少一个单元对图形。 从单元对图确定部分逆布局树。 对于部分逆布局树,仅考虑完整的反向布局树的分支,描述不同单元格的形状之间的交互。 从部分逆布局树生成数据集,并且例如通过使用部分逆布局树来保存数据集。

    Method for classifying errors in the layout of a semiconductor circuit
    10.
    发明申请
    Method for classifying errors in the layout of a semiconductor circuit 有权
    对半导体电路布局中的误差进行分类的方法

    公开(公告)号:US20070157142A1

    公开(公告)日:2007-07-05

    申请号:US11712635

    申请日:2007-03-01

    CPC classification number: G06F17/5081

    Abstract: A method for classifying errors in the layout of a semiconductor circuit includes examining the layout of the semiconductor circuit for infringement of predetermined design rules in order to establish errors. For each error, the error is marked in the layout, and information about the error and the layout of the semiconductor circuit in an area surrounding the error is extracted. The extracted information is compared with prestored information within a multiplicity of classes, and the error is assigned to the respective class on the basis of the compared information.

    Abstract translation: 用于对半导体电路的布局中的误差进行分类的方法包括:检查半导体电路的布局,以便违反预定的设计规则以建立错误。 对于每个错误,在布局中标记错误,并提取关于错误周围区域中的半导体电路的错误和布局的信息。 将所提取的信息与多个类中的预存信息进行比较,并且基于所比较的信息将错误分配给相应的类。

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