公开(公告)号：US5698900A

公开(公告)日：1997-12-16

申请号：US684734

申请日：1996-07-22

申请人： Christopher A. Bozada ,  Tony K. Quach ,  Kenichi Nakano ,  Gregory C. DeSalvo ,  G. David Via ,  Ross W. Dettmer ,  Charles K. Havasy ,  James S. Sewell ,  John L. Ebel ,  James K. Gillespie

发明人： Christopher A. Bozada ,  Tony K. Quach ,  Kenichi Nakano ,  Gregory C. DeSalvo ,  G. David Via ,  Ross W. Dettmer ,  Charles K. Havasy ,  James S. Sewell ,  John L. Ebel ,  James K. Gillespie

IPC分类号： H01L21/285 ,  H01L21/335 ,  H01L21/76 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L29/66462 ,  H01L21/28575 ,  H01L21/28581 ,  H01L21/7605 ,  H01L29/41775 ,  H01L29/42312 ,  H01L29/452 ,  H01L29/475

摘要： A periodic table group III-IV field-effect transistor device is described. The disclosed device uses a single metalization for ohmic and Schottky barrier contacts, permanent plural etch stop layers, employs a non-alloyed ohmic connection semiconductor layer and includes a permanent semiconductor material-comprised secondary mask element, a mask element which can be grown epitaxially during wafer fabrication to perform useful functions in both the device processing and device utilization environments. The device of the invention may be achieved with both an all optical lithographic process and a combined optical and electron beam lithographic process The disclosed device provides a field-effect transistor of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

摘要翻译： 描述了周期表III-IV族场效应晶体管器件。 所公开的器件使用单个金属化用于欧姆和肖特基势垒触点，永久多个蚀刻停止层，采用非合金欧姆连接半导体层，并且包括具有永久性半导体材料的次级掩模元件，可以外延生长的掩模元件 晶片制造以在器件处理和器件利用环境中执行有用的功能。 本发明的器件可以通过全光学光刻工艺和组合的光学和电子束光刻工艺实现。所公开的器件提供了降低制造成本，增加的尺寸精度和现有技术电性能的场效应晶体管。

公开(公告)号：US06653214B1

公开(公告)日：2003-11-25

申请号：US10034747

申请日：2002-01-03

申请人： Tony K. Quach ,  G. David Via ,  James S. Sewell ,  Christopher A. Bozada ,  Gregory C. DeSalvo ,  Ross W. Dettmer ,  John L. Ebel ,  James K. Gillespie ,  Thomas Jenkins ,  Kenichi Nakano

发明人： Tony K. Quach ,  G. David Via ,  James S. Sewell ,  Christopher A. Bozada ,  Gregory C. DeSalvo ,  Ross W. Dettmer ,  John L. Ebel ,  James K. Gillespie ,  Thomas Jenkins ,  Kenichi Nakano

IPC分类号： H01L2144

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated circuit substrate via-hole fabrication arrangement providing for accurate determination of via-hole size and via-hole registration through use of a calibrated pattern formed into the integrated circuit substrate during portions of the normal circuit fabrication process. Initiation of the via-hole and fabrication of the calibrated pattern from one surface, such as the front side, of the integrated circuit wafer and completion of the via-hole from the opposite surface of the wafer are contemplated. The calibrated pattern may be one of several possible physical configurations and of selected dimensions usable with the process, materials and circuitry of the device being fabricated. Use of the invention in fabricating ground conductor-connected via conductors for gigahertz radio frequency-capable integrated circuits of the monolithic or mixed hybrid with monolithic type and having a ground plane element is contemplated.

摘要翻译： 一种集成电路衬底通孔制造装置，其通过在正常电路制造工艺的部分期间通过使用形成在集成电路衬底中的校准图案来准确地确定通孔尺寸和通孔配准。 设想从集成电路晶片的一个表面（例如前侧）开始通孔并制造校准图案，并且从晶片的相对表面完成通孔。 校准图案可以是几个可能的物理配置中的一个以及可用于正在制造的设备的工艺，材料和电路的选定尺寸之一。 设想将本发明用于制造具有整体式或具有接地平面元件的单片或混合混合物的千兆赫兹无线电频率集成电路的接地导体连接通孔导体。

公开(公告)号：US5008542A

公开(公告)日：1991-04-16

申请号：US456924

申请日：1989-12-20

申请人： David C. Look ,  James S. Sewell ,  Millard G. Mier ,  John R. Sizelove ,  Dennis C. Walters ,  Scott C. Dudley

发明人： David C. Look ,  James S. Sewell ,  Millard G. Mier ,  John R. Sizelove ,  Dennis C. Walters ,  Scott C. Dudley

IPC分类号： G01N21/95

CPC分类号： G01N21/9505 ,  G01N21/9501 ,  G01N21/8803

摘要： A method and system for measuring whole-wafer etch pit density (.rho..sub.D) is disclosed in which an etch GaAs wafer is tested for fractional transmission at a plurality of points over its surface. The fractional transmission (T) of light through the wafer is detected, amplified and fed to a computer where at least two points of transmission measurement are selected for calibration. From these measurements, together with an estimate of the average etch pit size (area), the values for fractional transmission in regions of low etch pit density T.sub.O and high etch pit density T.sub.E may be calculated, and used to convert transmission data directly to etch pit density (.rho..sub.D) according to the equation ##EQU1##

摘要翻译： 公开了一种用于测量全晶圆蚀刻坑密度（rho D）的方法和系统，其中在其表面上的多个点测试蚀刻GaAs晶片进行分数透射。 通过晶片的光的分数透射（T）被检测，放大并馈送到其中选择至少两个透射测量点用于校准的计算机。 从这些测量结果以及平均蚀刻坑尺寸（面积）的估计值可以计算出低蚀刻坑密度TO和高蚀刻坑密度TE区域中的分数透射值，并用于将透射数据直接转换为蚀刻 凹坑密度（rho D）