公开(公告)号：US20180366557A1

公开(公告)日：2018-12-20

申请号：US15956477

申请日：2018-04-18

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Alexander Reznicek

IPC分类号： H01L29/66 ,  H01L29/739 ,  H01L29/165 ,  H01L29/423

CPC分类号： H01L29/66356 ,  H01L21/0257 ,  H01L29/0676 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0895 ,  H01L29/165 ,  H01L29/42312 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7311 ,  H01L29/7391

摘要： After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.

公开(公告)号：US20180342578A1

公开(公告)日：2018-11-29

申请号：US15916423

申请日：2018-03-09

申请人： Tsinghua University ,  HON HAI PRECISION INDUSTRY CO., LTD.

发明人： JIN ZHANG ,  YANG WEI ,  KAI-LI JIANG ,  SHOU-SHAN FAN

IPC分类号： H01L29/06 ,  H01L51/00 ,  H01L29/423 ,  H01L29/16 ,  B82Y30/00 ,  H01L21/02

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02425 ,  H01L21/02444 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/02631 ,  H01L27/04 ,  H01L29/1608 ,  H01L29/413 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/42312 ,  H01L29/66227 ,  H01L29/78687 ,  H01L51/0048 ,  H01L51/0562

摘要： A semiconductor device includes a gate electrode, an insulating layer, a first carbon nanotube, a second carbon nanotube, a P-type semiconductor layer, an N-type semiconductor layer, a conductive film, a first electrode, a second electrode and a third electrode. The insulating layer is located on a surface of the gate electrode. The first carbon nanotube and the second carbon nanotube are located on a surface of the insulating layer. The P-type semiconductor layer and the N-type semiconductor layer are located on the surface of the insulating layer and apart from each other. The conductive film is located on surfaces of the P-type semiconductor layer and the N-type semiconductor layer. The first electrode is electrically connected with the first carbon nanotube. The second electrode is electrically connected with the second carbon nanotube. The third electrode is electrically connected with the conductive film.

公开(公告)号：US20180315608A1

公开(公告)日：2018-11-01

申请号：US15889400

申请日：2018-02-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Bang-Tai Tang ,  Tai-Chun Huang

IPC分类号： H01L21/28 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

CPC分类号： H01L21/28247 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32155 ,  H01L21/823437 ,  H01L27/1288 ,  H01L29/42312 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

摘要： A semiconductor device and a method of forming the semiconductor device are disclosed. A method includes forming a gate stack over a semiconductor structure. The gate stack is recessed to form a first recess. A first dielectric layer is formed along a bottom and sidewalls of the first recess, the first dielectric layer having a first etch rate. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a second etch rate, the first etch rate being higher than the second etch rate. A third dielectric layer is formed over the second dielectric layer. An etch rate of a portion of the third dielectric layer is altered. The first dielectric layer, the second dielectric layer, and the third dielectric layer are recessed to form a second recess. A capping layer is formed in the second recess.

公开(公告)号：US20180308926A1

公开(公告)日：2018-10-25

申请号：US15960845

申请日：2018-04-24

申请人： Murata Manufacturing Co., Ltd.

发明人： Shinnosuke TAKAHASHI ,  Masayuki AOIKE

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/778 ,  H01L29/423 ,  H01L29/40

CPC分类号： H01L29/0619 ,  H01L21/76 ,  H01L21/76224 ,  H01L29/0626 ,  H01L29/1075 ,  H01L29/1083 ,  H01L29/205 ,  H01L29/405 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7783 ,  H01L29/7786

摘要： A semiconductor layer arranged on a semiconductor substrate includes an active region and an element isolation region that surrounds the first active region when viewed in plan. A field effect transistor is formed in the active region. A plurality of guard ring electrodes separated from each other affect a potential of the active region through the element isolation region. An interlayer insulating film is formed over the semiconductor layer, the field effect transistor, and the guard ring electrodes. At least one guard ring connection wiring formed on the interlayer insulating film electrically interconnects the plurality of guard ring electrodes.

公开(公告)号：US20180219106A1

公开(公告)日：2018-08-02

申请号：US15882955

申请日：2018-01-29

申请人： QROMIS, Inc.

发明人： Vladimir Odnoblyudov ,  Ozgur Aktas

IPC分类号： H01L29/808 ,  H01L29/20 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L29/808 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/12 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/41775 ,  H01L29/42312 ,  H01L29/66446 ,  H01L29/66893

摘要： A lateral junction field-effect transistor includes a substrate of a first conductivity type having a dopant concentration; a first semiconductor layer of the first conductivity type having a first dopant concentration lower than the dopant concentration and disposed on the substrate; a second semiconductor layer of a second conductivity type having a second dopant concentration, the second conductivity type being different from the first conductivity type, the second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer of the first conductivity type having a third dopant concentration, the third semiconductor layer disposed on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type having a fourth dopant concentration lower than the dopant concentration, the fourth semiconductor layer disposed on the third semiconductor layer; a source region and a drain region disposed in the second semiconductor layer and on opposite sides of the third semiconductor layer.

公开(公告)号：US09837522B2

公开(公告)日：2017-12-05

申请号：US14929856

申请日：2015-11-02

申请人： Infineon Technologies Austria AG

发明人： Gerhard Prechtl ,  Clemens Ostermaier ,  Oliver Haeberlen

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/10

CPC分类号： H01L29/7787 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/7783

摘要： There are disclosed herein various implementations of a III-Nitride bidirectional device. Such a bidirectional device includes a substrate, a back channel layer situated over the substrate, and a device channel layer and a device barrier layer situated over the back channel layer. The device channel layer and the device barrier layer are configured to produce a device two-dimensional electron gas (2DEG). In addition, the III-Nitride bidirectional device includes first and second gates formed on respective first and second depletion segments situated over the device barrier layer. The III-Nitride bidirectional device also includes a back barrier situated between the back channel layer and the device channel layer. A polarization of the back channel layer of the III-Nitride bidirectional device is substantially equal to a polarization of the device channel layer.

公开(公告)号：US09324807B1

公开(公告)日：2016-04-26

申请号：US14796142

申请日：2015-07-10

申请人： United Silicon Carbide, Inc.

发明人： Anup Bhalla ,  Leonid Fursin

IPC分类号： H01L29/16 ,  H01L29/10 ,  H01L29/167 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78 ,  H01L29/739 ,  H01L27/06

CPC分类号： H01L29/1608 ,  H01L27/0629 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/42312 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/861

摘要： A monolithically integrated MOS channel in gate-source shorted mode is used as a diode for the third quadrant conduction path for a power MOSFET. The MOS diode and MOSFET can be constructed in a variety of configurations including split-cell and trench. The devices may be formed of silicon carbide, gallium nitride, aluminum nitride, aluminum gallium nitride, diamond, or similar semiconductor. Low storage capacitance and low knee voltage for the MOS diode can be achieved by a variety of means. The MOS diode may be implemented with channel mobility enhancement materials, and/or have a very thin/high permittivity gate dielectric. The MOSFET gate conductor and MOS diode gate conductor may be made of polysilicon doped with opposite dopant types. The surface of the MOS diode dielectric may be implanted with cesium.

摘要翻译： 栅极源短路模式中的单片集成MOS沟道用作功率MOSFET的第三象限传导路径的二极管。 MOS二极管和MOSFET可以构造成各种配置，包括分裂电池和沟槽。 器件可以由碳化硅，氮化镓，氮化铝，氮化铝镓，金刚石或类似的半导体形成。 MOS二极管的低存储电容和低拐点电压可以通过各种手段实现。 MOS二极管可以用沟道迁移率增强材料来实现，和/或具有非常薄/高介电常数的栅极电介质。 MOSFET栅极导体和MOS二极管栅极导体可以由掺杂有相反掺杂剂类型的多晶硅制成。 MOS二极管电介质的表面可以注入铯。

公开(公告)号：US20160079446A1

公开(公告)日：2016-03-17

申请号：US14695428

申请日：2015-04-24

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hyun-min CHOI ,  Ju-youn KIM ,  Hyun-jo KIM ,  Mu-kyeng JUNG

IPC分类号： H01L29/94 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/36

CPC分类号： H01L29/94 ,  H01L29/36 ,  H01L29/42312 ,  H01L29/4966 ,  H01L29/517

摘要： A pumping capacitor is provided. The pumping capacitor includes a substrate, a P-type gate layer on the substrate, and a gate dielectric layer between the substrate and the P-type gate layer. The substrate includes an N-type well region and an N-type doping region in the N-type well region.

摘要翻译： 提供一个泵送电容器。 泵浦电容器包括衬底，衬底上的P型栅极层以及衬底和P型栅极层之间的栅极电介质层。 衬底包括N型阱区和N型阱区中的N型掺杂区。

公开(公告)号：US09117893B1

公开(公告)日：2015-08-25

申请号：US13759478

申请日：2013-02-05

申请人： Chenming Hu ,  Anupama Bowonder ,  Pratik Patel ,  Daniel Chou ,  Prashant Majhi

发明人： Chenming Hu ,  Anupama Bowonder ,  Pratik Patel ,  Daniel Chou ,  Prashant Majhi

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/778 ,  B82Y99/00

CPC分类号： H01L29/78 ,  B82Y99/00 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/165 ,  H01L29/42312 ,  H01L29/7391 ,  H01L29/778 ,  H01L29/7786

摘要： Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.

摘要翻译： 公开了隧道晶体管的几个实施例。 在一个实施例中，隧道晶体管包括半导体衬底，形成在半导体衬底中的源极区域，形成在半导体衬底中的漏极区域，包括金属栅极电极和栅极电介质的栅极堆叠，以及基本上 平行于金属栅极电极和栅极电介质之间的界面。 作为与金属栅极电极和栅极电介质之间的界面基本平行的隧道结的结果，与常规隧道晶体管相比，隧道晶体管的导通电流显着改善。 在另一个实施例中，隧道晶体管包括降低隧道晶体管的导通电压的异质结构。

公开(公告)号：US20140264448A1

公开(公告)日：2014-09-18

申请号：US13837856

申请日：2013-03-15

申请人： CAROL O. NAMBA ,  Po-Hsin Lin ,  Poust Sumiko ,  Ioulia Smorchkova ,  Michael Wojtowicz ,  Ronald Grundbacher

发明人： CAROL O. NAMBA ,  Po-Hsin Lin ,  Poust Sumiko ,  Ioulia Smorchkova ,  Michael Wojtowicz ,  Ronald Grundbacher

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L21/28114 ,  H01L21/0277 ,  H01L21/28123 ,  H01L21/28537 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/42312 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/78

摘要： A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device.

摘要翻译： 提供了一种用于形成化合物半导体器件的栅极接触的方法。 栅极接触由栅极接触部分和顶部或翼部接触部分形成。 该方法允许机翼接触部分的尺寸的可操作性，同时基于期望的操作频率保持门接触部分的尺寸。 这是通过在翼接触部分上提供一个或多个额外的导电材料工艺来实现的，以增加翼接触部分的横截面面积来减小栅极电阻，同时保持栅极接触部分的长度以维持栅极接触部分的工作频率 装置。