公开(公告)号：US08374038B2

公开(公告)日：2013-02-12

申请号：US12773503

申请日：2010-05-04

申请人： Chuan-Ying Yu ,  Chun-Hsiung Hung ,  Ken-Hui Chen

发明人： Chuan-Ying Yu ,  Chun-Hsiung Hung ,  Ken-Hui Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/0483

摘要： A method of erasing memory cells of a memory device includes programming memory cells if the erasing procedure is suspended. The erasing procedure can include pre-programming, erasing, and soft-programming of memory cells in a selected memory unit. If a suspend command is received, for example to allow for a read operation of memory cells of another unit of memory, the erasing procedure stops the pre-programming, erasing, or soft-programming, and proceeds with programming one or more memory cells of the memory unit that was being erased.

摘要翻译： 擦除存储器件的存储器单元的方法包括如果擦除过程被暂停，则对存储器单元进行编程。 擦除过程可以包括对所选存储器单元中的存储器单元的预编程，擦除和软编程。 如果接收到暂停命令，例如允许对另一个存储单元的存储单元进行读操作，则擦除过程停止预编程，擦除或软编程，并且继续编程一个或多个存储器单元 被擦除的内存单元。

公开(公告)号：US08094493B2

公开(公告)日：2012-01-10

申请号：US11271300

申请日：2005-11-10

申请人： Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

发明人： Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

IPC分类号： G11C11/34 ,  G11C7/02

CPC分类号： G11C16/28 ,  G11C16/04 ,  G11C16/0475 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50004 ,  G11C2211/5634

摘要： A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding reference line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).

摘要翻译： 公开了一种存储器件，其包括多个字线和以多个模式之一工作并耦合到至少一个字线的多个存储单元。 存储装置还包括多个参考线和参考单元。 每个参考单元对应于一个操作模式，为相应模式提供参考电流，并耦合到至少一个参考线。 来自参考单元的参考单元电流也可以与目标范围进行比较，并且如果在目标范围之外，可以相应地调整相应参考线上的电压电平，使得参考电流落在目标范围内（即，参考 当前修剪）。

公开(公告)号：US20110273936A1

公开(公告)日：2011-11-10

申请号：US12773503

申请日：2010-05-04

申请人： Chuan-Ying Yu ,  Chun-Hsiung Hung ,  Ken-Hui Chen

发明人： Chuan-Ying Yu ,  Chun-Hsiung Hung ,  Ken-Hui Chen

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/16 ,  G11C16/0483

摘要： A method of erasing memory cells of a memory device includes programming memory cells if the erasing procedure is suspended. The erasing procedure can include pre-programming, erasing, and soft-programming of memory cells in a selected memory unit. If a suspend command is received, for example to allow for a read operation of memory cells of another unit of memory, the erasing procedure stops the pre-programming, erasing, or soft-programming, and proceeds with programming one or more memory cells of the memory unit that was being erased.

摘要翻译： 擦除存储器件的存储器单元的方法包括如果擦除过程被暂停，则对存储器单元进行编程。 擦除过程可以包括对所选存储器单元中的存储器单元的预编程，擦除和软编程。 如果接收到暂停命令，例如允许对另一个存储单元的存储单元进行读操作，则擦除过程停止预编程，擦除或软编程，并且继续编程一个或多个存储器单元 被擦除的内存单元。

公开(公告)号：US07180782B2

公开(公告)日：2007-02-20

申请号：US11151168

申请日：2005-06-10

申请人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

发明人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

IPC分类号： G11C16/28

CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/5002

摘要： Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that are shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.

摘要翻译： 根据本发明的非易失性存储器电路提供具有通过互连导体线在一组读出放大器之间共享的多个参考单元的参考存储器。 每个参考存储器的较高数量的参考单元产生更大量的用于对多个源极线进行充电的电流。 多个源极线耦合到互连导体条，用于与耦合到主存储器阵列中的存储器单元的源极线的电容匹配。 在硅晶片出来之后，对由主存储器阵列中的源极线产生的电容的测量以及由参考阵列中的源极线产生的电容进行可选的修整。 电容匹配的另一校准是通过切割源极线的一部分或者将一部分添加到源极线来修剪耦合到互连导体条和参考存储器的源极线之一来实现的。

公开(公告)号：US20060267059A1

公开(公告)日：2006-11-30

申请号：US11137098

申请日：2005-05-25

申请人： Chuan-Ying Yu ,  Chun-Hsiung Hung ,  Su-Chueh Lo ,  Nai-Ping Kuo ,  Ken-Hui Chen

发明人： Chuan-Ying Yu ,  Chun-Hsiung Hung ,  Su-Chueh Lo ,  Nai-Ping Kuo ,  Ken-Hui Chen

IPC分类号： H01L29/94

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

摘要： A wordline driver cell, coupled to at least one wordline, includes at least one diffusion region and at least one wordline driver semiconductor switching device formed in the at least one diffusion region. The at least one wordline driver semiconductor switching device has a channel width that is arranged perpendicular to a longitudinal axis of the at least one wordline.

摘要翻译： 耦合到至少一个字线的字线驱动器单元包括形成在至少一个扩散区域中的至少一个扩散区域和至少一个字线驱动器半导体开关器件。 所述至少一个字线驱动器半导体开关器件具有垂直于所述至少一个字线的纵向轴线布置的沟道宽度。

公开(公告)号：US20060104113A1

公开(公告)日：2006-05-18

申请号：US11271300

申请日：2005-11-10

申请人： Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

发明人： Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

IPC分类号： G11C16/06

CPC分类号： G11C16/28 ,  G11C16/04 ,  G11C16/0475 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50004 ,  G11C2211/5634

摘要： A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding referece line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).

摘要翻译： 公开了一种存储器件，其包括多个字线和以多个模式之一工作并耦合到至少一个字线的多个存储单元。 存储装置还包括多个参考线和参考单元。 每个参考单元对应于一个操作模式，为相应模式提供参考电流，并耦合到至少一个参考线。 来自参考单元的参考单元电流也可以与目标范围进行比较，并且如果在目标范围之外，可以相应地调整相应参考线上的电压电平，使得参考电流落在目标范围内（即，参考 当前修剪）。

公开(公告)号：US20070069800A1

公开(公告)日：2007-03-29

申请号：US11233901

申请日：2005-09-23

申请人： Yi-Chun Shih ,  Chun Hung ,  Kuen-Long Chang ,  Chuan-Ying Yu

发明人： Yi-Chun Shih ,  Chun Hung ,  Kuen-Long Chang ,  Chuan-Ying Yu

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  H02M2003/071

摘要： A negative charge-pump circuit for flash memory includes a well, a pass-gate transistor, a well bias circuit and a negative voltage recovery circuit. The pass-gate transistor has a source, a drain and a gate. The well bias circuit controls the well to remain one of zero biased and reverse biased. The negative voltage recovery circuit is coupled to a negative recovery voltage and coupled to the pass-gate transistor to selectively provide the negative recovery voltage to the pass-gate transistor when the charge-pump circuit is disabled.

摘要翻译： 用于闪速存储器的负电荷泵电路包括阱，通栅晶体管，阱偏置电路和负电压恢复电路。 栅极晶体管具有源极，漏极和栅极。 阱偏置电路控制阱保持零偏置和反向偏置之一。 负电压恢复电路耦合到负恢复电压并且耦合到通栅晶体管，以在电荷泵电路被禁用时选择性地向通过栅极晶体管提供负恢复电压。

公开(公告)号：US09225240B2

公开(公告)日：2015-12-29

申请号：US12786122

申请日：2010-05-24

申请人： Chun-Hsiung Hung ,  Chuan-Ying Yu

发明人： Chun-Hsiung Hung ,  Chuan-Ying Yu

IPC分类号： G05F3/02 ,  G05F1/10 ,  H02M3/07

CPC分类号： H02M3/073

摘要： A method of generating a pumping voltage in an integrated circuit includes receiving an external clock signal from outside of the integrated circuit. The frequency of the received external clock signal is changed according to one or more modulation ratios, resulting in one or more respective modulated external clock signal. The external clock signal or one of the modulated external clock signals is then selected for use as a pump clock signal. The pump clock signal is used for driving the pump capacitance of a pump circuit for generating the pumping voltage.

摘要翻译： 在集成电路中产生泵浦电压的方法包括从集成电路的外部接收外部时钟信号。 接收到的外部时钟信号的频率根据一个或多个调制比而改变，导致一个或多个相应调制的外部时钟信号。 然后选择外部时钟信号或调制的外部时钟信号之一用作泵浦时钟信号。 泵时钟信号用于驱动泵电路的泵电容以产生泵浦电压。

公开(公告)号：US20110115551A1

公开(公告)日：2011-05-19

申请号：US12786122

申请日：2010-05-24

申请人： Chun-Hsiung Hung ,  Chuan-Ying Yu

发明人： Chun-Hsiung Hung ,  Chuan-Ying Yu

IPC分类号： G05F3/02

CPC分类号： H02M3/073

摘要： A method of generating a pumping voltage in an integrated circuit includes receiving an external clock signal from outside of the integrated circuit. The frequency of the received external clock signal is changed according to one or more modulation ratios, resulting in one or more respective modulated external clock signal. The external clock signal or one of the modulated external clock signals is then selected for use as a pump clock signal. The pump clock signal is used for driving the pump capacitance of a pump circuit for generating the pumping voltage.

摘要翻译： 在集成电路中产生泵浦电压的方法包括从集成电路的外部接收外部时钟信号。 接收到的外部时钟信号的频率根据一个或多个调制比而改变，导致一个或多个相应调制的外部时钟信号。 然后选择外部时钟信号或调制的外部时钟信号之一用作泵浦时钟信号。 泵时钟信号用于驱动泵电路的泵电容以产生泵浦电压。

公开(公告)号：US20070019470A1

公开(公告)日：2007-01-25

申请号：US11188505

申请日：2005-07-25

申请人： Chun-Hsiung Hung ,  Chuan-Ying Yu

发明人： Chun-Hsiung Hung ,  Chuan-Ying Yu

IPC分类号： G11C16/04

CPC分类号： G11C16/3468 ,  G11C16/12 ,  G11C16/3404

摘要： A flash based device in configured for soft programming to correct for over-erase effect; however, the soft programming current is limited so as not to exceed the current that can be supplied during soft programming. Additionally, the voltage on the source node of each cell on the flash based device is maintained at a non-zero level, in order to allow for the use fo a higher word line voltage, but help prevent an over soft programming effect.