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    Erase process for use in semiconductor memory device
    1.
    发明授权
    Erase process for use in semiconductor memory device 有权
    用于半导体存储器件的擦除过程

    公开(公告)号：US08374038B2

    公开(公告)日：2013-02-12

    申请号：US12773503

    申请日：2010-05-04

    申请人： Chuan-Ying Yu ,  Chun-Hsiung Hung ,  Ken-Hui Chen

    发明人： Chuan-Ying Yu ,  Chun-Hsiung Hung ,  Ken-Hui Chen

    IPC分类号： G11C11/34

    CPC分类号： G11C16/16 ,  G11C16/0483

    摘要： A method of erasing memory cells of a memory device includes programming memory cells if the erasing procedure is suspended. The erasing procedure can include pre-programming, erasing, and soft-programming of memory cells in a selected memory unit. If a suspend command is received, for example to allow for a read operation of memory cells of another unit of memory, the erasing procedure stops the pre-programming, erasing, or soft-programming, and proceeds with programming one or more memory cells of the memory unit that was being erased.

    摘要翻译： 擦除存储器件的存储器单元的方法包括如果擦除过程被暂停，则对存储器单元进行编程。 擦除过程可以包括对所选存储器单元中的存储器单元的预编程，擦除和软编程。 如果接收到暂停命令，例如允许对另一个存储单元的存储单元进行读操作，则擦除过程停止预编程，擦除或软编程，并且继续编程一个或多个存储器单元 被擦除的内存单元。

    ERASE PROCESS FOR USE IN SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    ERASE PROCESS FOR USE IN SEMICONDUCTOR MEMORY DEVICE 有权
    用于半导体存储器件的擦除工艺

    公开(公告)号：US20110273936A1

    公开(公告)日：2011-11-10

    申请号：US12773503

    申请日：2010-05-04

    申请人： Chuan-Ying Yu ,  Chun-Hsiung Hung ,  Ken-Hui Chen

    发明人： Chuan-Ying Yu ,  Chun-Hsiung Hung ,  Ken-Hui Chen

    IPC分类号： G11C16/16 ,  G11C16/04

    CPC分类号： G11C16/16 ,  G11C16/0483

    摘要： A method of erasing memory cells of a memory device includes programming memory cells if the erasing procedure is suspended. The erasing procedure can include pre-programming, erasing, and soft-programming of memory cells in a selected memory unit. If a suspend command is received, for example to allow for a read operation of memory cells of another unit of memory, the erasing procedure stops the pre-programming, erasing, or soft-programming, and proceeds with programming one or more memory cells of the memory unit that was being erased.

    摘要翻译： 擦除存储器件的存储器单元的方法包括如果擦除过程被暂停，则对存储器单元进行编程。 擦除过程可以包括对所选存储器单元中的存储器单元的预编程，擦除和软编程。 如果接收到暂停命令，例如允许对另一个存储单元的存储单元进行读操作，则擦除过程停止预编程，擦除或软编程，并且继续编程一个或多个存储器单元 被擦除的内存单元。

    Word line decoder circuit apparatus and method
    4.
    发明授权
    Word line decoder circuit apparatus and method 有权
    字线解码电路装置及方法

    公开(公告)号：US08638636B2

    公开(公告)日：2014-01-28

    申请号：US12816960

    申请日：2010-06-16

    申请人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    发明人： Shin-Jang Shen ,  Bo-Chang Wu ,  Chuan Ying Yu ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC分类号： G11C8/00

    CPC分类号： G11C16/16

    摘要： One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.

    摘要翻译： 该技术的一个实施例是一种装置，存储器集成电路。 存储器集成电路具有字线地址解码电路。 该电路允许选择单个字线以具有擦除电压。 解码器电路包括反相器和逻辑。 逆变器具有输入和控制字线的输出以执行擦除操作。 输入的电压范围在第一参考电压和第二电压基准之间延伸。 电压基准的示例是电压源和地。 在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。 解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。

    Apparatus of Supplying Power and Method Therefor
    6.
    发明申请
    Apparatus of Supplying Power and Method Therefor 有权
    供电装置及其方法

    公开(公告)号：US20110227552A1

    公开(公告)日：2011-09-22

    申请号：US12820422

    申请日：2010-06-22

    申请人： Chih-Ting Hu ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Wu-Chin Peng ,  Kuen-Long Chang ,  Ken-Hui Chen

    发明人： Chih-Ting Hu ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Wu-Chin Peng ,  Kuen-Long Chang ,  Ken-Hui Chen

    IPC分类号： G05F3/02

    CPC分类号： H02M3/07 ,  G11C5/145 ,  H02M2001/0032 ,  Y02B70/16

    摘要： A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing.

    摘要翻译： 提供电源装置和供电方法。 用于具有第一功率信号的系统中的装置包括辅助单元和电源装置。 辅助单元选择性地输出根据第一功率信号的至少一个维持信号。 电源装置输出第二电力信号，其中电源装置根据至少一个维持信号维持第二电力信号，例如处于非空闲状态，例如空闲或待机状态或其他合适的定时。

    Read source line compensation in a non-volatile memory
    7.
    发明授权
    Read source line compensation in a non-volatile memory 有权
    在非易失性存储器中读取源极线补偿

    公开(公告)号：US07180782B2

    公开(公告)日：2007-02-20

    申请号：US11151168

    申请日：2005-06-10

    申请人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

    发明人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

    IPC分类号： G11C16/28

    CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/5002

    摘要： Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that are shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.

    摘要翻译： 根据本发明的非易失性存储器电路提供具有通过互连导体线在一组读出放大器之间共享的多个参考单元的参考存储器。 每个参考存储器的较高数量的参考单元产生更大量的用于对多个源极线进行充电的电流。 多个源极线耦合到互连导体条，用于与耦合到主存储器阵列中的存储器单元的源极线的电容匹配。 在硅晶片出来之后，对由主存储器阵列中的源极线产生的电容的测量以及由参考阵列中的源极线产生的电容进行可选的修整。 电容匹配的另一校准是通过切割源极线的一部分或者将一部分添加到源极线来修剪耦合到互连导体条和参考存储器的源极线之一来实现的。