公开(公告)号：US20210175322A1

公开(公告)日：2021-06-10

申请号：US17019621

申请日：2020-09-14

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John L. MELANSON ,  Lei ZHU ,  Wai-Shun SHUM ,  Xiaofan FEI ,  Johann G. GABORIAU

IPC: H01L49/02 ,  H01L23/522 ,  H03F1/02

Abstract: A single integrated circuit may include a signal path configured to generate an output signal from an input signal, wherein the signal path includes an amplifier configured to drive the output signal, a direct-current-to-direct-current (DC-DC) power converter having a power inductor integrated in the single integrated circuit and configured to generate a supply voltage to the amplifier from a source voltage to the DC-DC power converter, and control circuitry for controlling operation of converter switches of the DC-DC power converter in order that the supply voltage tracks at least one among the input signal and the output signal.

公开(公告)号：US20200177167A1

公开(公告)日：2020-06-04

申请号：US16784392

申请日：2020-02-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Jing BAI ,  Tejasvi DAS ,  Xin ZHAO ,  Lei ZHU ,  Xiaofan FEI

IPC: H03K3/01 ,  H03K17/687

Abstract: A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

公开(公告)号：US20200036352A1

公开(公告)日：2020-01-30

申请号：US16181762

申请日：2018-11-06

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Lei ZHU ,  Tejasvi DAS ,  John L. MELANSON ,  Wai-shun Wilson SHUM ,  Jing BAI ,  Xin ZHAO ,  Xiaofan FEI

IPC: H03G3/30 ,  H03F3/217 ,  H03F3/187 ,  H03F3/387

Abstract: A system may include a digital modulator configured to modulate an input signal received at an input of the digital modulator to generate a modulated input signal at an output of the digital modulator, a digital gain element having a digital gain and coupled to the digital modulator, an open-loop Class-D amplifier coupled to an output of the digital modulator and configured to amplify the modulated input signal, wherein the open-loop Class-D amplifier is powered from a variable power supply having a variable supply voltage which is variable in response to one or more characteristics of the input signal, and a control circuit configured to control the digital gain to approximately cancel changes in an analog gain of the open-loop Class-D amplifier due to variation in the variable supply voltage in response to the one or more characteristics of the input signal.

公开(公告)号：US20190260377A1

公开(公告)日：2019-08-22

申请号：US16162960

申请日：2018-10-17

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Jing BAI ,  Tejasvi DAS ,  Xin ZHAO ,  Lei ZHU ,  Xiaofan FEI

IPC: H03K17/687 ,  H03K17/06 ,  G06F3/01

Abstract: A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

公开(公告)号：US20190259402A1

公开(公告)日：2019-08-22

申请号：US16170524

申请日：2018-10-25

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Masoud FARSHBAF ZINATI ,  Arun RAMANI ,  Amar VELLANKI ,  Xiaofan FEI

IPC: G10L19/032 ,  H03F3/183 ,  H03F3/217 ,  G10L19/008 ,  G10L19/26

Abstract: A method may include receiving a stream of serial pulse-density modulation (PDM) data representing a first channel of data synchronized with a rising edge of a clock associated with the serial PDM data and a second channel of data synchronized with a falling edge of the clock, wherein each of the first channel of data and the second channel of data include encoded datagrams wherein each encoded datagram comprises more than one digital bit, detecting an invalid state associated with the stream, and responsive to detecting the invalid state, determining boundaries of each encoded datagram of the stream based on where within the stream the invalid state occurred.

公开(公告)号：US20190115886A1

公开(公告)日：2019-04-18

申请号：US16133045

申请日：2018-09-17

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Tejasvi DAS ,  Alan Mark MORTON ,  Xin ZHAO ,  Lei ZHU ,  Xiaofan FEI ,  Johann G. GABORIAU ,  John L. MELANSON ,  Amar VELLANKI

IPC: H03G3/30 ,  H03F3/187 ,  H04R3/00

Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, wherein a first gain of the first path and a second gain of the second path are approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.