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    Systems and methods for analog processing of problem graphs having arbitrary size and/or connectivity
    11.
    发明授权
    Systems and methods for analog processing of problem graphs having arbitrary size and/or connectivity 有权

    公开(公告)号：US11348026B2

    公开(公告)日：2022-05-31

    申请号：US16778295

    申请日：2020-01-31

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Murray C. Thom ,  Aidan P. Roy ,  Fabian A. Chudak ,  Zhengbing Bian ,  William G. Macready ,  Robert B. Israel ,  Kelly T. R. Boothby ,  Sheir Yarkoni ,  Yanbo Xue ,  Dmytro Korenkevych

    IPC: G06N10/00

    Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.

    SYSTEMS AND METHODS FOR ANALOG PROCESSING OF PROBLEM GRAPHS HAVING ARBITRARY SIZE AND/OR CONNECTIVITY
    13.
    发明申请
    SYSTEMS AND METHODS FOR ANALOG PROCESSING OF PROBLEM GRAPHS HAVING ARBITRARY SIZE AND/OR CONNECTIVITY 审中-公开

    公开(公告)号：US20200167685A1

    公开(公告)日：2020-05-28

    申请号：US16778295

    申请日：2020-01-31

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Murray C. Thom ,  Aidan P. Roy ,  Fabian A. Chudak ,  Zhengbing Bian ,  William G. Macready ,  Robert B. Israel ,  Kelly T. R. Boothby ,  Sheir Yarkoni ,  Yanbo Xue ,  Dmytro Korenkevych

    IPC: G06N10/00

    Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.

    Sampling from a set of spins with clamping
    15.
    发明授权
    Sampling from a set of spins with clamping 有权
    从夹紧的一组旋转中取样

    公开(公告)号：US09588940B2

    公开(公告)日：2017-03-07

    申请号：US14676605

    申请日：2015-04-01

    Applicant: D-Wave Systems Inc.

    Inventor： Firas Hamze ,  James King ,  Evgeny Andriyash ,  Catherine McGeoch ,  Jack Raymond ,  Jason Rolfe ,  William G. Macready ,  Aaron Lott ,  Murray C. Thom

    IPC: G06F15/18 ,  G06F17/18 ,  G06N99/00

    CPC classification number: G06F17/18 ,  G06N99/002 ,  G06N99/005

    Abstract: The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples maybe used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor, and reading out states for the qubits. The states for the qubits in the plurality of qubits correspond to a sample from the probability distribution. Operation of the sampling device may be summarized as including updating a set of samples to include the sample from the probability distribution, and returning the set of samples.

    Abstract translation: 系统，设备，物品和方法通常涉及从可用概率分布中的采样。 样本可以用于创建期望的概率分布，例如用于计算技术中使用的计算值，包括：重要性采样和马尔可夫链蒙特卡洛系统。 模拟处理器可以作为采样发生器操作，例如通过以下方式来对模拟处理器进行编程：模拟处理器的可编程参数数量的配置，其对应于模拟处理器的量子位上的概率分布，演进模拟处理器， 并读出量子位的状态。 多个量子位中的量子位的状态对应于来自概率分布的样本。 采样装置的操作可以被概括为包括更新一组样本以包括来自概率分布的样本，并返回该组样本。

    Display screen or portion thereof with graphical user interface
    17.
    外观设计
    Display screen or portion thereof with graphical user interface 有权

    公开(公告)号：USD1002664S1

    公开(公告)日：2023-10-24

    申请号：US29725225

    申请日：2020-02-24

    Applicant: D-WAVE SYSTEMS INC.

    Designer： Fiona L. Hanington ,  Murray C. Thom ,  Dominic Wong ,  Jeffrey P. Johnston ,  Skyler J. Richter

    Abstract: FIG. 1 is a front view of a display screen or portion thereof with a graphical user interface, with a bounding shape surrounding a section thereof and a number corresponding to a detailed view of the corresponding section, showing our new design.
    FIG. 2 is a detailed front view of the section surrounded by the bounding shape of the display screen or portion thereof with the graphical user interface of FIG. 1, showing our new design.
    FIG. 3 is a front view of a display screen or portion thereof with graphical user interface, with a bounding shape surrounding a section thereof and a number corresponding to a detailed view of the corresponding section, showing our new design.
    FIG. 4 is a detailed front view of the section surrounded by the bounding shape of the display screen or portion thereof with the graphical user interface of FIG. 3, showing our new design.
    FIG. 5 is a front view of a display screen or portion thereof with graphical user interface, with a bounding shape surrounding a section thereof and a number corresponding to a detailed view of the corresponding section, showing our new design.
    FIG. 6 is a detailed front view of the section surrounded by the bounding shape of the display screen or portion thereof with the graphical user interface of FIG. 5, showing our new design.
    FIG. 7 is a front view of a display screen or portion thereof with graphical user interface, with a bounding shape surrounding a section thereof and a number corresponding to a detailed view of the corresponding section, showing our new design; and,
    FIG. 8 is a detailed front view of the section surrounded by the bounding shape of the display screen or portion thereof with the graphical user interface of FIG. 7, showing our new design.
    The outermost broken lines in FIGS. 1, 3, 5 and 7 illustrate a display screen or portion thereof and form no part of the claimed design. The broken lines with alternating long and short segments indicate bounding shapes of FIGS. 1, 3, 5 and 7 that are illustrated as enlarged detailed views in FIGS. 2, 4, 6, and 8, respectively. The remaining broken lines illustrate portions of the graphical user interface that form no part of the claimed design.

    SYSTEMS AND METHODS FOR ANALOG PROCESSING OF PROBLEM GRAPHS HAVING ARBITRARY SIZE AND/OR CONNECTIVITY
    18.
    发明申请
    SYSTEMS AND METHODS FOR ANALOG PROCESSING OF PROBLEM GRAPHS HAVING ARBITRARY SIZE AND/OR CONNECTIVITY 有权

    公开(公告)号：US20220335320A1

    公开(公告)日：2022-10-20

    申请号：US17739411

    申请日：2022-05-09

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Murray C. Thom ,  Aidan P. Roy ,  Fabian A. Chudak ,  Zhengbing Bian ,  William G. Macready ,  Robert B. Israel ,  Kelly T. R. Boothby ,  Sheir Yarkoni ,  Yanbo Xue ,  Dmytro Korenkevych

    IPC: G06N10/00

    Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.

    SYSTEMS, DEVICES, ARTICLES, AND METHODS FOR QUANTUM PROCESSOR ARCHITECTURE
    20.
    发明申请
    SYSTEMS, DEVICES, ARTICLES, AND METHODS FOR QUANTUM PROCESSOR ARCHITECTURE 审中-公开

    公开(公告)号：US20180246848A1

    公开(公告)日：2018-08-30

    申请号：US15549512

    申请日：2016-01-27

    Applicant: D-Wave Systems Inc.

    Inventor： Adam Douglass ,  Richard G. Harris ,  Trevor Michael Lanting ,  Andrew Douglas King ,  Jack Raymond ,  Murray C. Thom

    IPC: G06F15/80 ,  G06N99/00

    CPC classification number: G06F15/803 ,  G06N10/00

    Abstract: A topology or hardware graph of a quantum processor is modifiable, for example prior to embedding of a problem, for instance by creating chains of qubits, where each chain which operates as a single or logical qubit to impose a logical graph on the quantum processor. A user interface (UI) allows a user to select a topology suited for embedding a particular problem or type of problem, to supply parameters that define the desired topology, or to supply or specify a problem graph or problem definition from which a processor-based system determines or selects an appropriate topology or logical graph to impose. Topologies may have regularity and/or self-similarity over the quantum processor or portions thereof, which portions may constitute unit cells. Logical graphs imposed on the quantum processor may take the form of a hypercube graph. A UI allows the user to specify a desired dimension of the hypercube graph.

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