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1.发明授权公开(公告)号：US11797874B2
公开(公告)日：2023-10-24
申请号：US17387654
申请日：2021-07-28
Applicant: D-WAVE SYSTEMS INC.
Inventor： Paul I. Bunyk , James King , Murray C. Thom , Mohammad H. Amin , Anatoly Smirnov , Sheir Yarkoni , Trevor M. Lanting , Andrew D. King , Kelly T. R. Boothby
CPC classification number: G06N10/00 , G06F11/0736 , G06F11/0751 , G06F11/0793
Abstract: The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.
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公开(公告)号：US11537926B2
公开(公告)日：2022-12-27
申请号：US16741208
申请日：2020-01-13
Applicant: D-WAVE SYSTEMS INC.
Inventor： James A. King , William W. Bernoudy , Kelly T. R. Boothby , Pau Farré Pérez
Abstract: Systems and methods are described for operating a hybrid computing system using cluster contraction for converting large, dense input to reduced input that can be easily mapped into a quantum processor. The reduced input represents the global structure of the problem. Techniques involve partitioning the input variables into clusters and contracting each cluster. The input variables can be partitioned using an Unweighted Pair Group Method with Arithmetic Mean algorithm. The quantum processor returns samples based on the reduced input and the samples are expanded to correspond to the original input.
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公开(公告)号：US20210091062A1
公开(公告)日：2021-03-25
申请号：US17026740
申请日：2020-09-21
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T. R. Boothby
Abstract: This disclosure generally relates to processor systems comprising printed circuit boards, I/O chips and processor chips with mated contacts. Contacts are formed on an upper surface of a printed circuit board having a through-hole and on a processor chip inside the through-hole. The processor chip may be a superconducting quantum processor chip comprising qubits, couplers, Digital to Analog converters, QFP shift registers and analog lines. Contacts are formed on an upper surface on an I/O chip and mated with the contacts on the printed circuit board and the processor chip. Contacts may be Indium bump bonds or superconducting solder bonds. The processor chip and the I/O chip may include a shield layer, a substrate layer and a thermally conductive layer.
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公开(公告)号：US20200320424A1
公开(公告)日：2020-10-08
申请号：US16858108
申请日：2020-04-24
Applicant: D-WAVE SYSTEMS INC.
Inventor： Sheir Yarkoni , Trevor Michael Lanting , Kelly T. R. Boothby , Andrew Douglas King , Evgeny A. Andriyash , Mohammad H. Amin
Abstract: A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
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公开(公告)号：US10528886B2
公开(公告)日：2020-01-07
申请号：US15726239
申请日：2017-10-05
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T. R. Boothby
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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Patent Agency Ranking
公开(公告)号：US20240256930A1
公开(公告)日：2024-08-01
申请号：US18514482
申请日：2023-11-20
Applicant: D-WAVE SYSTEMS INC.
Inventor： Sheir Yarkoni , Trevor Michael Lanting , Kelly T. R. Boothby , Andrew Douglas King , Evgeny A. Andriyash , Mohammad H. Amin
Abstract: A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
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公开(公告)号：US11900216B2
公开(公告)日：2024-02-13
申请号：US17988250
申请日：2022-11-16
Applicant: D-WAVE SYSTEMS INC.
Inventor： James A. King , William W. Bernoudy , Kelly T. R. Boothby , Pau Farré Pérez
IPC: G06N10/00 , G06F17/18 , G06F18/21 , G06F18/23213
CPC classification number: G06N10/00 , G06F17/18 , G06F18/217 , G06F18/23213
Abstract: Systems and methods are described for operating a hybrid computing system using cluster contraction for converting large, dense input to reduced input that can be easily mapped into a quantum processor. The reduced input represents the global structure of the problem. Techniques involve partitioning the input variables into clusters and contracting each cluster. The input variables can be partitioned using an Unweighted Pair Group Method with Arithmetic Mean algorithm. The quantum processor returns samples based on the reduced input and the samples are expanded to correspond to the original input.
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公开(公告)号：US11730066B2
公开(公告)日：2023-08-15
申请号：US17399375
申请日：2021-08-11
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E. S. Johansson
CPC classification number: H10N60/124 , G06N10/00 , H10N60/805
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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公开(公告)号：US20220391081A1
公开(公告)日：2022-12-08
申请号：US17855095
申请日：2022-06-30
Applicant: D-WAVE SYSTEMS INC.
Inventor： Murray C. Thom , Fiona L. Hanington , Alexander Condello , William W. Bernoudy , Melody C. Wong , Aidan P. Roy , Kelly T. R. Boothby , Edward D. Dahl
IPC: G06F3/04847 , G06N10/00 , G06T11/20 , G06F3/04817 , G06F16/901
Abstract: A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.
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10.发明申请公开(公告)号：US20210263643A1
公开(公告)日：2021-08-26
申请号：US17182975
申请日：2021-02-23
Applicant: D-WAVE SYSTEMS INC.
Inventor： Murray C. Thom , Fiona L. Hanington , Alexander Condello , William W. Bernoudy , Melody C. Wong , Aidan P. Roy , Kelly T. R. Boothby , Edward D. Dahl
IPC: G06F3/0484 , G06N10/00 , G06F16/901 , G06T11/20 , G06F3/0481
Abstract: A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.
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