公开(公告)号：US07518817B1

公开(公告)日：2009-04-14

申请号：US11484864

申请日：2006-07-10

申请人： Arun Balakrishnan ,  John VanLaanen ,  Leo Lopez ,  John Shaw ,  Bruce D. Buch ,  Claud L. Blevins

发明人： Arun Balakrishnan ,  John VanLaanen ,  Leo Lopez ,  John Shaw ,  Bruce D. Buch ,  Claud L. Blevins

IPC分类号： G11B15/46

CPC分类号： G11B33/1493

摘要： A disk drive having reduced electromagnetic emission quasi-peaks is provided. The repetition rate of servo blocks or data is reduced, spread or otherwise altered. In one embodiment, the number of data zones is increased to achieve an emissions reduction goal. In one embodiment, the disk drive is configured to effectively have one track per zone. In one embodiment, the rotation rate of the disk is varied or the effective data bit density, as detected by the read/write head, is otherwise varied. In one embodiment, servo-sectors are intentionally positioned to vary the length, along the track, of inter-servo intervals.

摘要翻译： 提供具有减小的电磁发射准峰值的磁盘驱动器。 伺服块或数据的重复率降低，扩展或以其他方式改变。 在一个实施例中，增加了数据区的数量以实现减排目标。 在一个实施例中，盘驱动器被配置成每个区域有效地具有一个轨道。 在一个实施例中，盘的旋转速率是变化的，或者由读/写头检测到的有效数据位密度被改变。 在一个实施例中，伺服扇区被有意地定位成沿着轨道改变伺服间间隔的长度。

公开(公告)号：US06625781B2

公开(公告)日：2003-09-23

申请号：US09771100

申请日：2001-01-26

申请人： Wolfgang Roethig ,  Ganesh Lakshminarayana ,  Anand Raghunathan ,  Arun Balakrishnan

发明人： Wolfgang Roethig ,  Ganesh Lakshminarayana ,  Anand Raghunathan ,  Arun Balakrishnan

IPC分类号： G06F1750

CPC分类号： G06F17/5022 ,  G06F2217/78

摘要： The invention utilizes the linear complexity of orthogonal vectors to reduce the number of equations (or variables) to be solved. The present invention constructs a power model of a set of combinations of states without considering irrelevant combinations. The invention distinguishes between the switching direction on the input and the output pin. The invention considers state-dependency as a function of power consumed and depending on the paths through internal nodes. The model considers switching input pins that do not cause the output pin to switch to overcome inaccuracies caused by combining the power pin model with the state and arc power model with state. The model considers switching input pins that cause the output pin to switch. For cells in which the slewrate propagation effect from input to output is negligible, the invention uses a model of 2 power pins with state. The invention also determines the validity of this model. The present invention also models a power arc from one input pin to multiple output pins.

公开(公告)号：US6038102A

公开(公告)日：2000-03-14

申请号：US784559

申请日：1997-01-21

申请人： Arun Balakrishnan ,  Stephen P. Williams

发明人： Arun Balakrishnan ,  Stephen P. Williams

IPC分类号： G11B5/48 ,  G11B21/00

CPC分类号： G11B5/4853 ,  G11B21/00 ,  G11B5/486 ,  G11B5/484

摘要： A trace conductor array includes an electrically insulative support substrate and a plurality of electrical signal trace conductors formed along substantially parallel paths in a single layer on the substrate. The electrical signal trace conductors each have a plurality of spaced apart trace conductor segments. Passive electrical trace conductors are formed on the substrate in spaces between the spaced apart adjacent trace conductor segments, and are spaced apart and electrically isolated therefrom. The passive trace conductors generally follow a geometry of the spaced apart segments and thereby repel magnetic flux lines at higher frequencies and result in decoupling of the high frequency current-carrying conductor trace segments. A preferred application is for interconnecting a head and a preamplifier/drive circuit within a hard disk drive.

摘要翻译： 轨迹导体阵列包括电绝缘支撑衬底和沿衬底上单层中的基本平行路径形成的多个电信号迹线导体。 电信号迹线导体各自具有多个间隔开的迹线导体段。 无源电迹线导体在间隔开的相邻迹线导体段之间的空间中形成在衬底上，并且与其隔开并与之电绝缘。 无源迹线导体通常遵循间隔开的段的几何形状，从而以更高的频率排斥磁通线，并导致高频载流导体迹线段的去耦。 优选的应用是将磁头和前置放大器/驱动电路互连在硬盘驱动器内。

公开(公告)号：US06731467B1

公开(公告)日：2004-05-04

申请号：US10302533

申请日：2002-11-21

申请人： Arun Balakrishnan

发明人： Arun Balakrishnan

IPC分类号： G11B548

CPC分类号： G11B5/4853 ,  H05K1/024 ,  H05K2201/09236 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2203/0597

摘要： A tall-electrode trace interconnect array includes a dielectric support substrate for supporting least two tall-electrode trace conductors. A dielectric support structure on the support substrate supports outside longitudinal walls of the two tall-electrode trace conductors. The dielectric support structure is formed to be absent from a longitudinal space between the two tall-electrode trace conductors thereby defining an ambient air dielectric to reduce and control inter-electrode capacitance and increase resonant frequency and effective electrical bandwidth of the trace interconnect array. A method for forming the array is also disclosed.

摘要翻译： 高电极迹线互连阵列包括用于支撑最小二个高电极迹线导体的电介质支撑衬底。 支撑基板上的电介质支撑结构支撑两根高电极迹线导体的外侧纵向壁。 电介质支撑结构形成为不存在于两个高电极迹线导体之间的纵向空间中，从而限定环境空气电介质以减少并控制电极间电容并增加迹线互连阵列的谐振频率和有效电带宽。 还公开了一种形成阵列的方法。

公开(公告)号：US06424499B1

公开(公告)日：2002-07-23

申请号：US09283313

申请日：1999-03-31

申请人： Arun Balakrishnan ,  Gregory P. Hertrich ,  Mark Sheppard ,  Doug Gunther

发明人： Arun Balakrishnan ,  Gregory P. Hertrich ,  Mark Sheppard ,  Doug Gunther

IPC分类号： G11B548

CPC分类号： G11B5/4893

摘要： A flexible multi-channel trace interconnect array has a head end for electrically connecting write and read trace pairs respectively to write and read elements of a data transducer head, a body formed of a flexible dielectric material and carrying the write and read trace pairs, and at least one circuit end for connecting the write and read trace pairs respectively to write driver and read preamplifier circuits of a data storage device. Each trace pair includes two trace conductors each having a trace width, and an inter-conductor separation space. Adjacent trace pairs are separated by an inter-pair space having a width greater than, and preferably two to twenty times greater than the inter-conductor separation space in order to decouple adjacent channel pairs.

摘要翻译： 灵活的多通道跟踪互连阵列具有头端，用于将写入和读取跟踪对分别电连接到写入和读取数据传感器头的元件，由柔性电介质材料形成并承载写入和读取迹线对的元件，以及 至少一个用于将写入和读取跟踪对分别连接到数据存储设备的写入驱动器和读取前置放大器电路的电路端。 每个迹线对包括每个具有迹线宽度的两个迹线导体和导体间分隔空间。 相邻轨迹对被具有比导体间分隔空间大的宽度，优选地是二至二十倍的宽度的对间隔隔开，以便使相邻的沟道对分离。

公开(公告)号：US06275358B1

公开(公告)日：2001-08-14

申请号：US09266442

申请日：1999-03-11

申请人： Arun Balakrishnan ,  Christopher Carpenter

发明人： Arun Balakrishnan ,  Christopher Carpenter

IPC分类号： G11B548

CPC分类号： G11B21/00 ,  G11B5/4853 ,  G11B5/486

摘要： A conductor trace array includes an electrically insulative support substrate and a plurality of pairs of electrical signal conductor traces and a plurality of pairs of passive electrical conductor traces. All of the traces are formed along substantially parallel paths in a single layer on the substrate. Each pair of the electrical signal conductor traces is arranged on the support substrate such that they are positioned in a space defined between each pair of passive electrical conductor traces. As a result, each pair of signal conductor traces has a passive electrical conductor trace positioned immediately adjacent thereto. The passive conductor traces generally follow a geometry of the signal conductor traces and thereby form a capacitive coupling relationship therebetween. This capacitive coupling relationship increases the characteristic impedance of the signal conductor traces. A preferred application is for interconnecting a head and a preamplifier/drive circuit within a hard disk drive, wherein the interconnecting trace is expressly provided upon an E-block of the activator.

摘要翻译： 导体迹线阵列包括电绝缘支撑衬底和多对电信号导体迹线和多对无源电导体迹线。 所有迹线沿着基板上的单层中的基本上平行的路径形成。 每对电信号导体迹线布置在支撑基板上，使得它们被定位在限定在每对无源电导体迹线之间的空间中。 结果，每对信号导体迹线具有与之相邻的无源电导体迹线。 无源导体迹线通常遵循信号导体迹线的几何形状，从而在它们之间形成电容耦合关系。 该电容耦合关系增加了信号导体迹线的特性阻抗。 优选的应用是在硬盘驱动器内互连头部和前置放大器/驱动电路，其中互连迹线被明确地提供在激活器的E块上。

公开(公告)号：US06134687A

公开(公告)日：2000-10-17

申请号：US994430

申请日：1997-12-19

申请人： Srimat Chakradhar ,  Arun Balakrishnan

发明人： Srimat Chakradhar ,  Arun Balakrishnan

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318586

摘要： A method, system and a computer product for a new partial scan technique that incurs significantly less overhead than the full-scan technique and yet achieves very high test coverage in short CPU times are provided. Scan memory elements are selected so that the scanned circuit satisfies two key properties in the test mode. First, the scanned circuit has partitions that are peripherally interacting finite state machines (peripheral partitions). Second, the memory element dependency graph (S-graph) of each peripheral partition of the scanned circuit has a tree structure. An efficient for algorithm peripheral partitioning and tree decomposition is provided. The scan memory element selection algorithm iteratively partitions the S-graph into disjoint sub-graphs with the tree structure.

公开(公告)号：US5754369A

公开(公告)日：1998-05-19

申请号：US724978

申请日：1996-10-03

申请人： Arun Balakrishnan

发明人： Arun Balakrishnan

IPC分类号： G11B21/21 ,  G11B5/00 ,  G11B5/012 ,  G11B5/02 ,  G11B5/11 ,  G11B5/48 ,  G11B23/00 ,  G11B33/12 ,  G11B33/14 ,  G11B5/17

CPC分类号： G11B5/4853 ,  G11B5/012 ,  G11B5/02 ,  G11B5/486 ,  G11B2005/0016 ,  G11B23/0007 ,  G11B33/122 ,  G11B5/11 ,  G11B5/484

摘要： A head suspension has an integrated self-shielding trace conductor array for supporting and electrically interconnecting a dual element read/write head to electronic circuitry in a disk drive. Write traces are placed proximately to the read traces and are grounded during data reading operations in order to serve as a read trace electrostatic shield during the data reading operations.

摘要翻译： 磁头悬架具有集成的自屏蔽跟踪导体阵列，用于支持并将双元件读/写头电连接到磁盘驱动器中的电子电路。 写入迹线靠近读取迹线放置，并在数据读取操作期间接地，以便在数据读取操作期间用作读取迹线静电屏蔽。

公开(公告)号：US5737152A

公开(公告)日：1998-04-07

申请号：US720833

申请日：1996-10-03

申请人： Arun Balakrishnan

发明人： Arun Balakrishnan

IPC分类号： G11B21/21 ,  G11B5/39 ,  G11B5/48 ,  G11B21/16 ,  G11B23/00

CPC分类号： G11B5/4846 ,  G11B21/16 ,  G11B5/484 ,  G11B5/4853 ,  G11B5/486 ,  G11B23/0007 ,  G11B5/3967

摘要： A head suspension has an integrated multi-layer trace conductor array for supporting and electrically interconnecting a read/write head to electronic circuitry in a disk drive. The electrical micro strip transmission line characteristics of the conductor array is controlled by the selective placement and connection of the trace paths within the multiple layers in order to control and balance electrical parameters including array inductance, inter-trace capacitance, and trace capacitance to a ground plane. The ground plane may further comprise a solid sheet of material or an arrangement of grounded traces disposed in proximity to signal-carrying traces of the micro strip transmission line in order to control and obtain desired electrical characteristics.

摘要翻译： 磁头悬架具有集成的多层迹线导体阵列，用于支持并将读/写电头互连到磁盘驱动器中的电子电路。 导体阵列的电微带传输线特性通过多层中的迹线路径的选择性放置和连接来控制，以便控制和平衡包括阵列电感，迹线间电容和对地的迹线电容的电参数 飞机 接地平面可以进一步包括固体材料片或布置在接近微带传输线的信号载体迹线附近的接地迹线的布置，以便控制和获得期望的电特性。

公开(公告)号：US20140112918A1

公开(公告)日：2014-04-24

申请号：US14122922

申请日：2012-05-30

申请人： Veena Agarwal ,  Arun Balakrishnan ,  Giridharan Periyasamy

发明人： Veena Agarwal ,  Arun Balakrishnan ,  Giridharan Periyasamy

IPC分类号： A61K31/4025 ,  A61K31/517 ,  A61K31/513 ,  A61K31/337 ,  A61K39/395 ,  A61K31/44 ,  A61K33/24

CPC分类号： A61K31/4025 ,  A61K31/282 ,  A61K31/337 ,  A61K31/44 ,  A61K31/513 ,  A61K31/517 ,  A61K33/24 ,  A61K39/39558 ,  A61K2300/00

摘要： The present invention relates to a pharmaceutical combination for use in the treatment of squamous cell carcinoma, comprising a CDK inhibitor selected from the compounds of formula (I); or a pharmaceutically acceptable salt thereof and one or more antineoplastic agents selected from sorafenib, lapatinib, erlotinib, cisplatin, 5-fluorouracil, docetaxel or cetuximab or a pharmaceutically acceptable salt thereof. The said pharmaceutical combination exhibits synergy when used in the treatment of squamous cell carcinoma of head and neck (SCCHN). The invention also relates to a pharmaceutical composition comprising the said combination and a method for the treatment of squamous cell carcinoma of head and neck (SCCHN), using a therapeutically effective amount of said combination.

摘要翻译： 本发明涉及用于治疗鳞状细胞癌的药物组合物，其包含选自式（I）化合物的CDK抑制剂; 或其药学上可接受的盐和选自索拉非尼，拉帕替尼，厄洛替尼，顺铂，5-氟尿嘧啶，多西紫杉醇或西妥昔单抗或其药学上可接受的盐的一种或多种抗肿瘤剂。 当用于治疗头颈鳞状细胞癌（SCCHN）时，所述药物组合显示出协同作用。 本发明还涉及包含所述组合的药物组合物和使用治疗有效量的所述组合治疗头颈部鳞状细胞癌（SCCHN）的方法。