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11.发明申请公开(公告)号：US20090180584A1
公开(公告)日：2009-07-16
申请号：US12175534
申请日：2008-07-18
申请人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
发明人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译： 本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。 该电路包括连接到移位寄存器的输入和输出的选择器。 选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。 连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。 控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。 控制装置还包括从电路外部可访问的数据输出。 观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。 当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。
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12.发明申请MULTI-BANK RANDOM ACCESS MEMORY STRUCTURE WITH GLOBAL AND LOCAL SIGNAL BUFFERING FOR IMPROVED PERFORMANCE 有权具有全球和本地信号缓存的多银行随机存取存储器结构，用于改进性能公开(公告)号：US20130315022A1
公开(公告)日：2013-11-28
申请号：US13479448
申请日：2012-05-24
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G11C5/025 , G11C7/10 , G11C7/1048 , G11C7/18 , G11C8/12
摘要： Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.
摘要翻译： 公开了多库随机存取存储器（RAM）结构的实施例，其在全局和本地连接器级提供信号缓冲以提高性能。 具体来说，逆变器被并入到全局连接器中，该连接器遍历存储体组并且从存储器控制器传送信号（例如，地址信号，控制信号和/或数据信号），并且还转换成局部的交替组 连接器，其将全局连接器上的节点连接到对应的存储体组，使得由存储器控制器经由全局和本地连接器的存储器组接收的任何信号由偶数个反相器缓冲 并且因此是真实的信号。 在全局和本地连接器级别的信号缓冲都会导致相对较快的转换速度，较短的传播延迟和低峰值功耗，同时面积消耗量的增加也会降低。
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公开(公告)号：US07911820B2
公开(公告)日：2011-03-22
申请号：US12176543
申请日：2008-07-21
申请人： Darren L. Anand , John A. Fifield , John R. Goss
发明人： Darren L. Anand , John A. Fifield , John R. Goss
IPC分类号： G11C17/16
摘要： An apparatus for regulating eFUSE programming current includes a current control generator receiving an input reference current through a first current path of reference fuses, the input reference current proportional to a desired eFUSE programming current; a second current path including a reference programming FET and a second group of reference fuses; and a voltage comparator coupled to a gate terminal of the reference programming FET so as to adjust the gate voltage of the reference programming FET to equalize a first voltage across the first current path with a second voltage across the second current path. The gate voltage of the reference programming FET is an output of the current control generator, coupled to corresponding gates of one or more selected programming devices of an eFUSE array such that the selected programming devices source the desired eFUSE programming current to a selected eFUSE to be programmed.
摘要翻译： 用于调节eFUSE编程电流的装置包括电流控制发生器，其通过参考熔丝的第一电流路径接收输入参考电流，所述输入参考电流与期望的eFUSE编程电流成比例; 包括参考编程FET和第二组参考保险丝的第二电流路径; 以及耦合到参考编程FET的栅极端子的电压比较器，以便调整参考编程FET的栅极电压，以跨越第二电流路径的第二电压来平衡跨越第一电流路径的第一电压。 参考编程FET的栅极电压是电流控制发生器的输出，耦合到eFUSE阵列的一个或多个选定的编程设备的相应门，使得所选择的编程设备将所选择的eFUSE编程电流输出到所选择的eFUSE为 程序。
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公开(公告)号：US07061304B2
公开(公告)日：2006-06-13
申请号：US10707963
申请日：2004-01-28
申请人： Darren L. Anand , John A. Fifield
发明人： Darren L. Anand , John A. Fifield
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： A fuse latch circuit with a current reference generator is described where the resistive switch point of the latch is stabilized against effects of manufacturing processing, operating voltage and temperature. A digital control word is used to select the desired resistive trip point of the fuse latch and compensation within the reference generator maintains this resistive trip point with high accuracy. The variable resistive trip point is set to a first value at test and then to a second value in use condition to enhance operating margin, and soft error immunity.
摘要翻译： 描述了具有电流参考发生器的保险丝锁存电路，其中闩锁的电阻开关点对制造处理，工作电压和温度的影响是稳定的。 使用数字控制字来选择熔丝锁存器的期望电阻跳变点，并且参考发生器内的补偿以高精度维持该电阻跳变点。 可变电阻跳变点在测试时被设置为第一个值，然后在使用条件下设置为第二个值，以提高运算裕度和软误差抗扰度。
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15.发明授权Method and circuit for precise timing of signals in an embedded DRAM array 失效用于嵌入式DRAM阵列中信号精确定时的方法和电路公开(公告)号：US06944090B2
公开(公告)日：2005-09-13
申请号：US10604184
申请日：2003-06-30
申请人： Darren L. Anand , John A. Fifield , Harold Pilo
发明人： Darren L. Anand , John A. Fifield , Harold Pilo
CPC分类号： G11C29/50012 , G11C11/401 , G11C29/02 , G11C2029/0401 , G11C2029/1204
摘要： A method and circuit for timing the start of a precharge period in an eDRAM. The circuit including: a delayed lock loop circuit for receiving a clock signal and generating a control signal for adjusting an internal delay of the clock signal; and means for generating a delayed clock signal in response to the control signal. The means for generating the delayed clock signal is a multiple stage delay circuit, each stage of the multiple delay stage circuit connected in series and each stage individually responsive to the control signal.
摘要翻译： 一种用于定时在eDRAM中预充电期间开始的方法和电路。 该电路包括：延迟锁定环电路，用于接收时钟信号并产生用于调整时钟信号的内部延迟的控制信号; 以及用于响应于控制信号产生延迟的时钟信号的装置。 用于产生延迟时钟信号的装置是多级延迟电路，多级延迟级电路的每级串联连接，每级分别响应控制信号。
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16.发明授权公开(公告)号：US07916826B2
公开(公告)日：2011-03-29
申请号：US12175534
申请日：2008-07-18
申请人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
发明人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译： 本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。 该电路包括连接到移位寄存器的输入和输出的选择器。 选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。 连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。 控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。 控制装置还包括从电路外部可访问的数据输出。 观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。 当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。
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公开(公告)号：US07089136B2
公开(公告)日：2006-08-08
申请号：US10604414
申请日：2003-07-18
IPC分类号： G01R31/00
摘要： An electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output of the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain when the next fuse(s) is not to be blown. Accordingly, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.
摘要翻译： 一种电熔丝回路设计，用于减少用冗余eFuse电路制造的半导体器件的测试时间。 除了熔丝锁存器和图案锁存器之外，每个eFuse电路还提供一对二路复用器（MUX）。 保险丝图案锁存器中存储有要熔断保险丝的信息。 模式锁存器的输出与程序输入进行“与”运算以提供MUX的选择信号。 基于选择信号，MUX允许移位的“1”进入移位链中的下一个锁存器，或者在下一个保险丝不被熔断时，旁路下一个锁存器或锁存在换档链中。 因此，本发明仅能够使与熔断器相关联的熔丝锁存器保持被转换的“1”传播到下一个eFuse电路。
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18.发明授权Reference generator with programmable M and B parameters and methods of use 有权具有可编程M和B参数的参考发生器和使用方法公开(公告)号：US08773920B2
公开(公告)日：2014-07-08
申请号：US13401368
申请日：2012-02-21
申请人： Darren L. Anand , John A. Fifield
发明人： Darren L. Anand , John A. Fifield
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , Y10T307/718
摘要： A reference generator with programmable m and b parameters and methods of use are provided. A circuit includes a first generator operable to generate a first voltage including a fraction of a supply voltage. The circuit further includes a second generator operable to generate a second voltage. The circuit further includes a mixer and buffer circuit operable to output a reference voltage including a sum of the first and second voltages.
摘要翻译： 提供了具有可编程m和b参数和使用方法的参考发生器。 电路包括可操作以产生包括电源电压的一部分的第一电压的第一发生器。 电路还包括可操作以产生第二电压的第二发生器。 该电路还包括可操作以输出包括第一和第二电压之和的参考电压的混频器和缓冲电路。
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公开(公告)号：US20100014373A1
公开(公告)日：2010-01-21
申请号：US12176543
申请日：2008-07-21
申请人： Darren L. Anand , John A. Fifield , John R. Goss
发明人： Darren L. Anand , John A. Fifield , John R. Goss
摘要： An apparatus for regulating eFUSE programming current includes a current control generator receiving an input reference current through a first current path of reference fuses, the input reference current proportional to a desired eFUSE programming current; a second current path including a reference programming FET and a second group of reference fuses; and a voltage comparator coupled to a gate terminal of the reference programming FET so as to adjust the gate voltage of the reference programming FET to equalize a first voltage across the first current path with a second voltage across the second current path. The gate voltage of the reference programming FET is an output of the current control generator, coupled to corresponding gates of one or more selected programming devices of an eFUSE array such that the selected programming devices source the desired eFUSE programming current to a selected eFUSE to be programmed.
摘要翻译： 用于调节eFUSE编程电流的装置包括电流控制发生器，其通过参考熔丝的第一电流路径接收输入参考电流，所述输入参考电流与期望的eFUSE编程电流成比例; 包括参考编程FET和第二组参考保险丝的第二电流路径; 以及耦合到参考编程FET的栅极端子的电压比较器，以便调整参考编程FET的栅极电压，以跨越第二电流路径的第二电压来平衡跨越第一电流路径的第一电压。 参考编程FET的栅极电压是电流控制发生器的输出，耦合到eFUSE阵列的一个或多个选定的编程设备的相应门，使得所选择的编程设备将所选择的eFUSE编程电流输出到所选择的eFUSE为 程序。
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20.发明申请公开(公告)号：US20090158092A1
公开(公告)日：2009-06-18
申请号：US11958680
申请日：2007-12-18
CPC分类号： G01R19/16552 , G11C11/401 , G11C29/02 , G11C29/021 , G11C29/44 , G11C2029/0401 , G11C2029/4402
摘要： The status of multiple on-chip power supply systems is indicated for use in modifying chip test flow and diagnosing chip failure. Digital compliance signals are received, each compliance signal associated with one of multiple on-chip power supplies. Each power supply has an associated compliance level, and each compliance signal indicates whether its associated power supply is operating at the associated compliance level. The compliance signals are converted into a power supply status signal indicating status of the compliance signals associated with the power supply. The power supply status signal is output. If a power supply is operating at its associated compliance level, the output power supply status signal indicates that the power supply is passing. If the power supply is not operating at its associated compliance level, the output power supply status signal indicates that the power supply is failing. If a power supply is failing, a memory test may be aborted, simplifying chip failure diagnosis.
摘要翻译： 多片式电源系统的状态被指示用于修改芯片测试流程和诊断芯片故障。 接收数字符合性信号，每个合规信号与多个片上电源之一相关联。 每个电源具有相关的合规级别，并且每个合规信号指示其相关联的电源是否以相关联的合规级别运行。 合规信号被转换成指示与电源相关联的符合性信号的状态的电源状态信号。 输出电源状态信号。 如果电源工作在相关的合规级别，则输出电源状态信号表示电源正在通过。 如果电源不在其相关的合规级别运行，则输出电源状态信号表示电源出现故障。 如果电源出现故障，可能会中断内存测试，从而简化了芯片故障诊断。
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