公开(公告)号：US06205462B1

公开(公告)日：2001-03-20

申请号：US09414322

申请日：1999-10-06

申请人： David C. Wyland ,  David A. Harrison

发明人： David C. Wyland ,  David A. Harrison

IPC分类号： G06F744

CPC分类号： G06F7/5443 ,  G06F2207/3824

摘要： Disclosed is a Multiply-Accumulate circuit that includes an exponent adder circuit, a mantissa multiplier circuit, a shifter, a full adder, and an accumulator. The product adder circuit receives two operands in a special combined data format which prescribes a mantissa and an exponent for both integer and floating point operands. The exponent adder circuit adds the exponents of the two operands. But if before the addition the exponent adder circuit detects an integer as an operand, it replaces the exponent of the integer by a substitute value in that addition. This substitute value is related to the number of bits of the mantissa of the integer. The mantissa multiplier circuit multiplies the two mantissas of the two operands. The shifter shifts the resultant product of multiplication into a pre-defined fixed point format according to the resultant sum of the addition generated by the exponent adder circuit. The full adder adds this shifted product to the current content of the accumulator.

摘要翻译： 公开了一种乘法累加电路，其包括指数加法器电路，尾数乘法器电路，移位器，全加器和累加器。 产品加法器电路以特殊的组合数据格式接收两个操作数，它们规定了整数和浮点操作数的尾数和指数。 指数加法器电路将两个操作数的指数相加。 但是如果在加法之前，指数加法器电路检测一个整数作为一个操作数，它将以该加法代替整数的指数。 该替代值与整数的尾数的位数有关。 尾数乘法器电路将两个操作数的两个奇数相乘。 移位器根据由指数加法器电路产生的加法结果之和将乘积乘积的乘积移位到预定义的固定点格式。 全加器将此移位乘积加到累加器的当前内容。

公开(公告)号：US07225216B1

公开(公告)日：2007-05-29

申请号：US10192391

申请日：2002-07-09

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： G06F7/52

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F2207/3884

摘要： Aspects for performing a multiply-accumulate operation on floating point numbers in a single clock cycle are described. These aspects include mantissa logic for combining a mantissa portion of floating point inputs and exponent logic coupled to the mantissa logic. The exponent logic adjusts the combination of an exponent portion of the floating point inputs by a predetermined value to produce a shift amount and allows pipeline stages in the mantissa logic, wherein an unnormalized floating point result is produced from the mantissa logic on each clock cycle.

摘要翻译： 描述在单个时钟周期中对浮点数进行乘法累加运算的方面。 这些方面包括用于组合浮点输入的尾数部分和耦合到尾数逻辑的指数逻辑的尾数逻辑。 指数逻辑将浮点输入的指数部分的组合调整预定值以产生移位量并允许尾数逻辑中的流水线级，其中在每个时钟周期上从尾数逻辑产生非归一化浮点结果。

公开(公告)号：US06931466B2

公开(公告)日：2005-08-16

申请号：US09968581

申请日：2001-09-28

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： G06F13/38 ,  G06F13/40 ,  G06F13/00 ,  G06F13/14

CPC分类号： G06F13/4068 ,  G06F13/385

摘要： Disclosed is a reprogrammable I/O system for a chip or board system that can be reprogrammed to simulate many I/O interfaces in firmware. The reprogrammable I/O system comprises an I/O cluster, an I/O bus, I/O pins, and logic at the I/O pins. The I/O pins are arranged logically in a row and are grouped into pin groups of eight pins. Each pin group also includes a pin state machine (PSM) and a data FIFO coupled together. Each PSM has chain connections to the two neighboring PSM's. Each data FIFO has chain connections to the two neighbor data FIFO's. The reprogrammable I/O system allows firmware to organize the I/O pins into I/O interfaces. The firmware in PSM's and the I/O cluster that control the operations of the I/O pins can be changed (reprogrammed) so that the I/O system can perform other different interfaces.

摘要翻译： 公开了一种用于芯片或电路板系统的可重编程I / O系统，可重新编程以模拟固件中的许多I / O接口。 可编程I / O系统包括I / O集群，I / O总线，I / O引脚和I / O引脚上的逻辑。 I / O引脚在逻辑上排成一行，并分为八个引脚的引脚组。 每个引脚组还包括一个引脚状态机（PSM）和一个连接在一起的数据FIFO。 每个PSM具有到两个相邻PSM的链路连接。 每个数据FIFO具有到两个相邻数据FIFO的链路连接。 可编程I / O系统允许固件将I / O引脚组织成I / O接口。 可以更改（重新编程）PSM中的固件和控制I / O引脚操作的I / O集群，以便I / O系统可以执行其他不同的接口。

公开(公告)号：US06836869B1

公开(公告)日：2004-12-28

申请号：US10061500

申请日：2002-02-01

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： H03M1315

CPC分类号： H03M13/09 ,  H03M13/1515 ,  H03M13/158 ,  H03M13/6513 ,  H03M13/6561

摘要： An error checking circuit that performs RS encoding and decoding operations and also generates CRC codes includes a configurable two-stage combinatorial circuit that carries out selected finite-field arithmetic operations associated with RS and CRC coding. Input registers store the generator polynomial and operand coefficients associated with the data blocks or packets being encoded or decoded, and an output register holds the intermediate working result and at the end the final result of the finite-field arithmetic operation. Each stage of the combinatorial circuit includes sets of AND and XOR gates performing bitwise finite-field multiply and add on the operand bits, and the connections between registers and gates and between gates in the two stages are configured by multiplexer units responsive to RS and CRC instructions. The two-stage combinatorial block can be replicated into a 4-stage or 8-stage arithmetic circuit for CRC mode.

摘要翻译： 执行RS编码和解码操作并且还生成CRC代码的错误检查电路包括可配置的两级组合电路，其执行与RS和CRC编码相关联的选定的有限域算术运算。 输入寄存器存储与被编码或解码的数据块或分组相关联的生成多项式和操作数系数，并且输出寄存器保持中间工作结果，并在结束时保持有限域算术运算的最终结果。 组合电路的每一级都包括AND和XOR门的组合，它们执行逐位有限域的乘法运算，并将其加到操作数位上，两级之间的寄存器和门之间以及门之间的连接由响应于RS和CRC的复用器单元配置 说明。 两级组合块可以复制到用于CRC模式的4级或8级运算电路。

公开(公告)号：US06556063B2

公开(公告)日：2003-04-29

申请号：US09772448

申请日：2001-01-29

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： H03K17687

CPC分类号： H03K17/693 ,  H03K17/04106 ,  H03K17/04113

摘要： A fast switching device for passing or blocking signals between two input/output ports includes a transistor having a first and a second terminal and a control terminal. The first and second terminals are connected between the two ports. The transistor passes signals between the ports when the transistor is turned on and blocks the passage of signals between the ports when the transistor is turned off. The resistance between the first and second terminals is less than about 10 ohms when the transistor is turned on. The device further includes a driver for controlling the control terminal of the transistor for turning it on or off. Preferably the capacitance between the first or second terminal and a reference potential is less than about 50 pF.

摘要翻译： 用于在两个输入/输出端口之间通过或阻塞信号的快速开关装置包括具有第一和第二端子和控制端子的晶体管。 第一和第二端子连接在两个端口之间。 当晶体管导通时，晶体管在端口之间传递信号，并且在晶体管截止时阻止端口之间的信号通过。 当晶体管导通时，第一和第二端子之间的电阻小于约10欧姆。 该装置还包括用于控制晶体管的控制端以使其接通或断开的驱动器。 优选地，第一或第二端子与参考电位之间的电容小于约50pF。

公开(公告)号：US5261064A

公开(公告)日：1993-11-09

申请号：US940744

申请日：1992-09-08

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： G06F5/10 ,  G06F5/16 ,  G06F7/62 ,  G06F12/00

CPC分类号： G06F5/16 ,  G06F5/10 ,  G06F7/62 ,  G11C7/1075 ,  G11C8/04 ,  G11C8/12

摘要： A high speed dual-port burst access memory (BAM) is disclosed that is capable of operating in both a burst access mode and random access mode simultaneously. The architecture of the high speed BAM permits random or burst access read or write operations on one port while simultaneously supporting sequential reading or writing in a burst or random mode of operation on a second port. Burst access can also be stopped and restarted for any number of clock cycles independently at each port. The BAM can also be configured as a high speed FIFO.

摘要翻译： 公开了一种高速双端口突发存取存储器（BAM），其能够同时在突发存取模式和随机存取模式下工作。 高速BAM的架构允许在一个端口上进行随机或突发存取读取或写入操作，同时支持以第二端口的突发或随机操作模式进行顺序读取或写入。 也可以在每个端口独立地停止并重新启动任何数量的时钟周期的突发访问。 BAM也可以配置为高速FIFO。

公开(公告)号：US20160380627A1

公开(公告)日：2016-12-29

申请号：US14747886

申请日：2015-06-23

申请人： David C. Wyland ,  Jonathan Alan Dutra

发明人： David C. Wyland ,  Jonathan Alan Dutra

IPC分类号： H03K17/567 ,  H03K5/1534

CPC分类号： H03K17/567 ,  H03K5/1534 ,  H03K17/04123 ,  H03K17/6877

摘要： A large-power insulated gate switching device (e.g., MOSFET) is used for driving relatively large surges of pulsed power through a load. The switching device has a relatively large gate capacitance which is difficult to quickly discharge. A gate charging and discharging circuit is provided having a bipolar junction transistor (BJT) configured to apply a charging voltage to charge the gate of the switching device where the BJT is configured to also discontinue the application of the charging voltage. An inductive circuit having an inductor is also provided. The inductive circuit is coupled to the gate of the switching device and further coupled to receive the charging voltage such that application of the charging voltage to the inductive circuit is with a polarity that induces a first current to flow through the inductor in a direction corresponding to charge moving away from the gate and such that discontinuation of the application of the charging voltage to the inductive circuit induces a second current flowing through the inductor in the direction corresponding to charge moving away from the gate such that the second current discharges the gate of the switching device. Faster turn off of the switching device is thus made possible and is synchronized to the discontinuation of the charging voltage.

摘要翻译： 大功率绝缘栅极开关器件（例如，MOSFET）用于通过负载驱动相对较大的脉冲功率浪涌。 开关器件具有相对较大的栅极电容，难以快速放电。 提供了具有双极结型晶体管（BJT）的栅极充电和放电电路，该双极结型晶体管被配置为对BJT配置的中断施加充电电压的开关器件的栅极施加充电电压。 还提供了具有电感器的感应电路。 感应电路耦合到开关器件的栅极，并进一步耦合以接收充电电压，使得对感应电路施加充电电压具有极性，其引起第一电流沿对应于 电荷远离栅极移动并且使得不断向感应电路施加充电电压引起在对应于从栅极移开的电荷的方向上流过电感器的第二电流，使得第二电流放电到栅极 开关装置。 因此，切换装置的更快的关闭成为可能，并且与停止充电电压同步。

公开(公告)号：US06208195B1

公开(公告)日：2001-03-27

申请号：US08934322

申请日：1997-09-19

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： H03K17687

CPC分类号： H03K17/693 ,  H03K17/04106 ,  H03K17/04113 ,  H03K17/6872

摘要： An integrated circuit fast transmission switching device is provided which comprises a first input/output lead having a bus capacitance Cb; a second input/output lead having a bus capacitance Cb; a first bidirectional field-effect transistor having an internal resistance Ri and an internal capacitance Ci including a first input/output terminal and a second input/output terminal and a gate terminal, said first terminal being connected to said first lead and said second terminal being connected to said second lead, so as to pass bidirectional external data signals between said first and second leads when said transistor is turned on and so as to block the passage of external data signals between said first and second leads when said transistor is turned off; wherein Ri and Ci for the field-effect transistor are such that Ri(Ci+Cb) is less than 6.5 nanoseconds; and a driver circuit including an external terminal for receiving an external on/off control signal; wherein said driver circuit is connected to the gate terminal so as to provide an internal on/off control signal to said gate terminal of said field-effect transistor.

摘要翻译： 提供一种集成电路快速传输切换装置，其包括具有总线电容Cb的第一输入/输出引线; 具有总线电容Cb的第二输入/输出引线; 具有内部电阻Ri和包括第一输入/输出端子和第二输入/输出端子和栅极端子的内部电容Ci的第一双向场效应晶体管，所述第一端子连接到所述第一引线和所述第二端子 连接到所述第二引线，以便当所述晶体管导通时在所述第一和第二引线之间传递双向外部数据信号，并且当所述晶体管截止时阻止所述第一和第二引线之间的外部数据信号的通过; 其中用于场效应晶体管的Ri和Ci使得Ri（Ci + Cb）小于6.5纳秒; 以及包括用于接收外部开/关控制信号的外部端子的驱动器电路; 其中所述驱动器电路连接到所述栅极端子，以便向所述场效应晶体管的所述栅极端提供内部开/关控制信号。

公开(公告)号：US5440715A

公开(公告)日：1995-08-08

申请号：US44543

申请日：1993-04-06

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： G06F17/30 ,  G11C15/00 ,  G06F12/00

CPC分类号： G06F17/30982 ,  G11C15/00

摘要： Apparatus and a method for easily expanding the effective width of the data words of a CAM without significantly increasing the basic width of the data storage registers or comparand register. A plurality of comparison blocks each include a register for data words having a predetermined width. Each data word includes a start bit, which indicates that a data word is the first data word of a much larger data word (or data line), and a chain bit, which indicates that a match has occurred between part of a comparand and the data word stored in the register. A maskable comparator provides a match output signal. The start bit is initially loaded into the chain-bit register for a data word. A latch is provided for storing the value of the chain bit from a preceding register into the chain-bit register of a following register. A priority encoder receives the match output signals from each of the comparators of the comparison blocks to identify the highest-priority comparison block, and the corresponding data line.

摘要翻译： 用于容易地扩展CAM的数据字的有效宽度的装置和方法，而不显着增加数据存储寄存器或比较寄存器的基本宽度。 多个比较块各自包括具有预定宽度的数据字的寄存器。 每个数据字包括起始位，其表示数据字是大得多的数据字（或数据线）的第一个数据字，以及指示匹配在比较器的一部分和 数据字存储在寄存器中。 可屏蔽比较器提供匹配输出信号。 起始位最初被加载到数据字的链 - 位寄存器中。 提供锁存器，用于将来自前一个寄存器的链码的值存储到后续寄存器的链 - 位寄存器中。 优先编码器从比较块的每个比较器接收匹配输出信号，以识别最高优先级比较块和对应的数据线。

公开(公告)号：US4882709A

公开(公告)日：1989-11-21

申请号：US236552

申请日：1988-08-25

申请人： David C. Wyland

发明人： David C. Wyland

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407

CPC分类号： G11C7/109 ,  G11C7/00 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/00

摘要： To provide a means for the safe, premature, abortion of a write cycle without additional, read cycle, pipeline delays multiplexers and registers are included configured to store the address and data signals externally developed during a write cycle and to store in a RAM array the stored data at the stored address during the next write cycle. A comparator is included, configured to compare each stored address with each current address. Also included is a multiplexer configured to, during a read cycle, provide from the RAM array the currently addressed data when the current address is different than the stored address and to, during a read cycle, provide the register stored data when the current address matches the stored address.