公开(公告)号：US07730338B2

公开(公告)日：2010-06-01

申请号：US12111828

申请日：2008-04-29

申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

IPC分类号： G06F1/00

CPC分类号： G11C5/147 ,  G11C5/025 ,  G11C11/4074

摘要： A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.

摘要翻译： 提供了存储器电路电源管理系统和方法。 在使用中，接口电路与多个存储器电路和系统通信。 接口电路可操作以将存储器电路和系统接口以与至少一部分存储器电路相关联地自主地执行功率管理操作。

公开(公告)号：US20080126689A1

公开(公告)日：2008-05-29

申请号：US11929432

申请日：2007-10-30

申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

IPC分类号： G06F9/455 ,  G06F12/00

CPC分类号： G11C7/1072 ,  G06F13/4243 ,  G11C7/10 ,  G11C11/406 ,  G11C11/40618 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.

公开(公告)号：US20080028137A1

公开(公告)日：2008-01-31

申请号：US11828182

申请日：2007-07-25

申请人： Keith R. Schakel ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

发明人： Keith R. Schakel ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang

IPC分类号： G06F13/28

CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C11/40611 ,  G11C11/40618

摘要： One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

摘要翻译： 一个实施例提出了一种接口电路，其被配置为管理刷新命令序列，其包括适于从存储器控制器接收刷新命令的系统接口，时钟频率检测电路被配置为确定向两个或多个存储器件耦合的交错刷新命令的发送定时 基于从存储器控制器接收的刷新命令到接口电路，以及被配置为生成用于两个或更多个存储器设备的交错刷新命令的至少两个刷新命令序列输出

公开(公告)号：US20080027702A1

公开(公告)日：2008-01-31

申请号：US11461420

申请日：2006-07-31

申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

IPC分类号： G06F13/10

CPC分类号： G11C11/406 ,  G11C7/10 ,  G11C11/40618

摘要： A system and method are provided for simulating a different number of memory circuits. Included is an interface circuit in communication with a first number of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit of a second number. Further, the interface circuit interfaces a majority of address or control signals of the memory circuits.

摘要翻译： 提供了一种用于模拟不同数量的存储器电路的系统和方法。 包括与第一数量的存储器电路和系统通信的接口电路。 这种接口电路可操作以将存储器电路和系统接口以模拟第二数量的至少一个存储器电路。 此外，接口电路接口存储器电路的大多数地址或控制信号。

公开(公告)号：US20080027697A1

公开(公告)日：2008-01-31

申请号：US11553372

申请日：2006-10-26

申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

IPC分类号： G06F17/50

CPC分类号： G11C11/406 ,  G11C7/10 ,  G11C11/40618

摘要： A system and method are provided including a component in communication with a plurality of memory circuits and a system. The component is operable to interface the memory circuits an the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The component is further operable to perform a power saving operation.

摘要翻译： 提供了一种包括与多个存储器电路和系统通信的部件的系统和方法。 该组件可操作以使存储器电路和系统接口，用于模拟至少一个与至少一个存储器电路的至少一个方面不同的方面的存储器电路。 该部件进一步可操作以执行省电操作。

公开(公告)号：US20080025122A1

公开(公告)日：2008-01-31

申请号：US11461437

申请日：2006-07-31

申请人： Keith R. Schakel ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

发明人： Keith R. Schakel ,  Suresh Natarajan Rajan ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40618 ,  G11C11/4093

摘要： A system and method are provided. In response to the receipt of a refresh control signal, a plurality of refresh control signals is sent to the memory circuits at different times.

摘要翻译： 提供了一种系统和方法。 响应于接收到刷新控制信号，在不同的时间将多个刷新控制信号发送到存储器电路。

公开(公告)号：US20080025108A1

公开(公告)日：2008-01-31

申请号：US11461430

申请日：2006-07-31

申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C8/18 ,  G11C5/04 ,  G11C7/1066 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40618 ,  G11C29/50012

摘要： A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.

摘要翻译： 提供了一种用于将从系统传送的信号延迟到多个存储器电路的系统和方法。 包括与多个存储器电路和系统通信的部件。 这样的组件可操作以从系统接收信号并且在延迟之后将该信号传送到至少一个存储器电路。 在其他实施例中，组件可操作以从至少一个存储器电路接收信号，并在延迟之后将该信号传送到系统。

公开(公告)号：US09632929B2

公开(公告)日：2017-04-25

申请号：US11672924

申请日：2007-02-08

申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

IPC分类号： G06F13/00 ,  G06F12/02 ,  G06F13/42 ,  G06F13/28 ,  G11C11/406 ,  G11C11/4093

CPC分类号： G06F12/0292 ,  G06F13/28 ,  G06F13/4243 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4093 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

公开(公告)号：US08667312B2

公开(公告)日：2014-03-04

申请号：US13471283

申请日：2012-05-14

申请人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

发明人： Suresh Natarajan Rajan ,  Keith R. Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

IPC分类号： G06F1/00

CPC分类号： G11C5/147 ,  G11C5/025 ,  G11C11/4074

摘要： A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits.

摘要翻译： 提供了存储器电路电源管理系统和方法。 接口电路与多个存储器电路和系统通信。 在使用中，接口电路可操作以仅与存储器电路的一部分相关联地执行功率管理操作。

公开(公告)号：US08631193B2

公开(公告)日：2014-01-14

申请号：US13473827

申请日：2012-05-17

申请人： Michael John Sebastian Smith ,  Suresh Natarajan Rajan ,  David T Wang

发明人： Michael John Sebastian Smith ,  Suresh Natarajan Rajan ,  David T Wang

IPC分类号： G06F12/00

CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

摘要： One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

摘要翻译： 本发明的一个实施例提出了一种抽象存储器子系统，其包括抽象存储器，每个存储器子系统可被配置为将存储器相关特性呈现到存储器系统接口上。 该特性可以通过逻辑信号或协议交换在存储器系统接口上呈现，并且特征可以包括地址空间，协议，存储器类型，功率管理规则，多个流水线级中的任何一个或多个， 多个银行，映射到物理银行，多个等级，定时特征，地址解码选项，总线周转时间参数，附加信号断言，子秩，多个平面或其他存储器 - 相关特征 一些实施例包括智能寄存器装置和/或智能缓冲器装置。 所公开的子系统的一个优点是可以优化存储器性能，而不管底层存储器硬件设备使用的特定协议。