公开(公告)号：US08631193B2

公开(公告)日：2014-01-14

申请号：US13473827

申请日：2012-05-17

申请人： Michael John Sebastian Smith ,  Suresh Natarajan Rajan ,  David T Wang

发明人： Michael John Sebastian Smith ,  Suresh Natarajan Rajan ,  David T Wang

IPC分类号： G06F12/00

CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

摘要： One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

摘要翻译： 本发明的一个实施例提出了一种抽象存储器子系统，其包括抽象存储器，每个存储器子系统可被配置为将存储器相关特性呈现到存储器系统接口上。 该特性可以通过逻辑信号或协议交换在存储器系统接口上呈现，并且特征可以包括地址空间，协议，存储器类型，功率管理规则，多个流水线级中的任何一个或多个， 多个银行，映射到物理银行，多个等级，定时特征，地址解码选项，总线周转时间参数，附加信号断言，子秩，多个平面或其他存储器 - 相关特征 一些实施例包括智能寄存器装置和/或智能缓冲器装置。 所公开的子系统的一个优点是可以优化存储器性能，而不管底层存储器硬件设备使用的特定协议。

公开(公告)号：US08089795B2

公开(公告)日：2012-01-03

申请号：US11702981

申请日：2007-02-05

申请人： Suresh N. Rajan ,  Keith R Schakel ,  Michael J. S. Smith ,  David T Wang ,  Frederick Daniel Weber

发明人： Suresh N. Rajan ,  Keith R Schakel ,  Michael J. S. Smith ,  David T Wang ,  Frederick Daniel Weber

IPC分类号： G11C5/06

CPC分类号： G11C11/4093 ,  G06F12/00 ,  G11C5/00 ,  G11C7/10 ,  G11C7/1045 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. In still other embodiments, the buffer circuit interfaces the memory stack to the host system for configuring one or more of the DRAM integrated circuits in the memory stack. Neither the patentee nor the USPTO intends for details set forth in the abstract to constitute limitations to claims not explicitly reciting those details.

摘要翻译： 包括至少一个存储器堆栈的存储器模块包括多个DRAM集成电路和接口电路。 接口电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为单个DRAM集成电路。 在其他实施例中，存储器模块包括至少一个存储器堆栈和缓冲器集成电路。 耦合到主机系统的缓冲器集成电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为至少两个DRAM集成电路。 在其他实施例中，接口电路以虚线方式将虚拟地址从主机系统映射到DRAM集成电路的物理地址。 在另一个实施例中，接口电路将来自主机系统的一个或多个虚拟地址组映射到DRAM集成电路的单个地址。 在其他实施例中，缓冲电路将存储器堆栈接口到主机系统，用于在DRAM集成电路和主机系统之间转换一个或多个物理参数。 在其他实施例中，缓冲电路将存储器堆栈接口到主机系统，用于配置存储器堆叠中的一个或多个DRAM集成电路。 专利权人和美国专利商标局均不打算在摘要中规定的细节构成对明确陈述这些细节的权利要求的限制。

公开(公告)号：US08619452B2

公开(公告)日：2013-12-31

申请号：US11515223

申请日：2006-09-01

申请人： Suresh N. Rajan ,  Michael J. S. Smith ,  David T Wang

发明人： Suresh N. Rajan ,  Michael J. S. Smith ,  David T Wang

IPC分类号： G11C5/02

CPC分类号： G11C7/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4093 ,  G11C29/812

摘要： Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.