公开(公告)号：US20110167297A1

公开(公告)日：2011-07-07

申请号：US12683147

申请日：2010-01-06

Applicant: Jianghui Su ,  Deqiang Song ,  Dawei Huang ,  Muthukumar Vairavan

Inventor： Jianghui Su ,  Deqiang Song ,  Dawei Huang ,  Muthukumar Vairavan

IPC: G06F11/07 ,  G06F11/00

CPC classification number: H04L7/0054 ,  H04L7/0062 ,  H04L7/0334

Abstract: A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.

Abstract translation: 描述接收机电路。 在接收机电路中，模数转换器（ADC）基于第一时钟信号产生数据信号的第一采样，并且时钟数据恢复（CDR）错误检测电路产生数据信号的第二采样 基于第二时钟信号。 另外，CDR错误检测电路估计来自第二样本中相邻的后续样本的第二样本中的当前样本的符号间干扰（ISI）。 基于第二样本和估计的ISI，CDR电路产生第一时钟信号和第二时钟信号，其涉及修改这些时钟信号中的一个或两者的偏差，使得当前采样与a的零交叉相关联 接收数据信号的通信信道的脉冲响应，从而减少或消除来自相邻的随后样本的ISI。

公开(公告)号：US20100208855A1

公开(公告)日：2010-08-19

申请号：US12388223

申请日：2009-02-18

Applicant: Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

Inventor： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

IPC: H04L7/00

CPC classification number: H04L7/0062

Abstract: A system and methods for recovering data from an input data signal are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver uses an adaptive algorithm to determine update signals for a pre-cursor tap coefficient of the FIR based on samples taken from the received data signal and conveys the update signals to the FIR. To generate update signals, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel. The phase is based on a clock recovered from the data signal. The update signals increase or decrease a pre-cursor tap coefficient setting in response to determining that the phase corresponds to a point earlier or later, respectively, than the peak amplitude of the channel's pulse response.

Abstract translation: 公开了一种从输入数据信号中恢复数据的系统和方法。 该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。 接收机使用自适应算法，基于从接收到的数据信号中取出的样本来确定FIR的前置光标抽头系数的更新信号，并将更新信号传送到FIR。 为了产生更新信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。 该相位基于从数据信号恢复的时钟。 响应于确定相位对应于分别比通道的脉冲响应的峰值幅度更早或更晚的点，更新信号增加或减少前置光标抽头系数设置。

公开(公告)号：US20100141340A1

公开(公告)日：2010-06-10

申请号：US12327865

申请日：2008-12-04

Applicant: Dawei Huang ,  Arif Amin ,  Waseem Ahmad ,  Rajesh Kumar ,  Venkatesh Arunachalam

Inventor： Dawei Huang ,  Arif Amin ,  Waseem Ahmad ,  Rajesh Kumar ,  Venkatesh Arunachalam

IPC: H03F3/45 ,  H03G3/30 ,  H04L25/49

CPC classification number: H03G1/0029 ,  H03F3/45197 ,  H03F2200/411 ,  H03F2200/453 ,  H03F2203/45491 ,  H03F2203/45492 ,  H03F2203/45494 ,  H03F2203/45511 ,  H03F2203/45652 ,  H03F2203/45702 ,  H04L25/0272

Abstract: A two stage fully differential amplifier has been designed which works, in tandem with a TX-FIR, as a linear equalizer at low frequencies, not covered by the TX-FIR, and also acts as a linear amplifier at higher frequencies which are equalized by the TX-FIR. The amplifier as a frequency response which does not attenuate signals frequencies less than one twentieth of baud rate, creates gain peaking ion the region between one twentieth and one tenth of baud rate and maintains flat peak gain up to half of baud rate. Different aspects of the frequency response curve (such as dc gain, max gain and zero frequency) are completely programmable. Also, the differential amplifier has been designed from low power and process, voltage and temperature insensitive frequency response.

Abstract translation: 已经设计了一个两级全差分放大器，它与TX-FIR一起作为低频的线性均衡器工作，不被TX-FIR覆盖，并且还作为较高频率的线性放大器，它们被均衡 TX-FIR。 作为频率响应的放大器，其不会衰减信号频率小于波特率的二十分之一，从而使波峰率的二分之一到十分之一的区域产生增益峰值，并将平坦的峰值增益保持在一半以上的波特率。 频率响应曲线（如直流增益，最大增益和零频率）的不同方面是完全可编程的。 此外，差分放大器是从低功耗和工艺，电压和温度不敏感的频率响应设计的。

公开(公告)号：US07225392B2

公开(公告)日：2007-05-29

申请号：US10090371

申请日：2002-03-04

Applicant: Dawei Huang ,  Feng Qi

Inventor： Dawei Huang ,  Feng Qi

IPC: H03M13/03

CPC classification number: H03M13/23

Abstract: The present invention discloses a system and method for channel coding data within a digital communication system. A data receiving circuit receives a digital input data sequence and periodically inserts known symbols, such as zeros, into the digital input data sequence as part of a convolutional zero code of the present invention. It forms an expanded digital input data sequence. An encoder is operatively connected to the data receiving circuit and trellis encodes the expanded sequence to produce a channel coded data stream such that the number of connections between trellis nodes in a trellis are reduced.

Abstract translation: 本发明公开了一种在数字通信系统内对数据进行信道编码的系统和方法。 数据接收电路接收数字输入数据序列，并且将已知的诸如零的符号周期地插入到数字输入数据序列中作为本发明的卷积零代码的一部分。 它形成一个扩展的数字输入数据序列。 编码器可操作地连接到数据接收电路，并对扩展的序列进行网格编码以产生信道编码的数据流，使得网格中网格节点之间的连接数量减少。

公开(公告)号：US08744024B2

公开(公告)日：2014-06-03

申请号：US13245533

申请日：2011-09-26

Applicant: Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Osman Javed ,  Hongtao Zhang

Inventor： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Osman Javed ,  Hongtao Zhang

IPC: H04L1/00

CPC classification number: H04L7/0054 ,  H04L7/0062

Abstract: In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(−1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample.

Abstract translation: 在接收机电路中，节点接收从发射机电路传送数据的信号。 此外，接收机电路中的时钟数据恢复（CDR）电路从接收到的信号中恢复一个速率时钟信号。 CDR电路恢复时钟信号，而不会将信号的第一脉冲响应前兆相对于信号的脉冲响应光标收敛到大约零（例如，随着第一脉冲响应前兆h（-1）收敛到非零， - 零值）。 此外，第一脉冲响应前体对应于除了当前样本以外的脉冲响应的至少一个前体或后脉冲。

公开(公告)号：US08634500B2

公开(公告)日：2014-01-21

申请号：US13431009

申请日：2012-03-27

Applicant: Zuxu Qin ,  Rajesh Kumar ,  Dawei Huang ,  Jing Shi ,  Deqiang Song

Inventor： Zuxu Qin ,  Rajesh Kumar ,  Dawei Huang ,  Jing Shi ,  Deqiang Song

IPC: H03K9/00

CPC classification number: H04L25/062 ,  H04L2025/0349

Abstract: A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.

Abstract translation: 接收器电路包括耦合以从信号路径接收数据信号的第一限幅器和与信号路径分离的参考电压路径的参考电压。 第一限幅器被配置为基于数据信号的电压与参考电压之间的比较来输出逻辑值。 接收器电路还包括被配置为产生参考电压的参考电压发生器。 参考电压发生器被配置为基于在第一模式中的操作期间先前接收到的信号的逻辑值来动态地产生参考电压。 在第二模式的操作期间，参考电压发生器被配置为产生并提供参考电压作为静态电压。

公开(公告)号：US20130259162A1

公开(公告)日：2013-10-03

申请号：US13431009

申请日：2012-03-27

Applicant: Zuxu Qin ,  Rajesh Kumar ,  Dawei Huang ,  Jing Shi ,  Deqiang Song

Inventor： Zuxu Qin ,  Rajesh Kumar ,  Dawei Huang ,  Jing Shi ,  Deqiang Song

IPC: H04L25/10 ,  H04B1/16

CPC classification number: H04L25/062 ,  H04L2025/0349

Abstract: A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.

Abstract translation: 接收器电路包括耦合以从信号路径接收数据信号的第一限幅器和与信号路径分离的参考电压路径的参考电压。 第一限幅器被配置为基于数据信号的电压与参考电压之间的比较来输出逻辑值。 接收器电路还包括被配置为产生参考电压的参考电压发生器。 参考电压发生器被配置为基于在第一模式中的操作期间先前接收到的信号的逻辑值来动态地产生参考电压。 在第二模式的操作期间，参考电压发生器被配置为产生并提供参考电压作为静态电压。

公开(公告)号：US08542764B2

公开(公告)日：2013-09-24

申请号：US12353717

申请日：2009-01-14

Applicant: Dong J. Yoon ,  Dawei Huang ,  Drew G. Doblar

Inventor： Dong J. Yoon ,  Dawei Huang ,  Drew G. Doblar

IPC: H04L27/00

CPC classification number: H03M9/00 ,  H03K3/00 ,  H03L7/0814

Abstract: A system and method include a SerDes transmitter comprising a digital block operating in a digital voltage domain. The digital block can be configured to receive a first group of bits of data in parallel and store history bits from another group of data. The SerDes transmitter can further comprise an analog block operating in an analog voltage domain. The analog block can be configured to receive the first group of bits of data from the digital block, receive the history bits from the digital block, generate a plurality of combinations of bits with one or more bits from the first group of bits and zero or more bits from the history bits, align each combination of bits to a phase of a multi-phase clock; and input each combination into an output driver.

Abstract translation: 一种系统和方法包括一个SerDes发射机，其包括以数字电压域工作的数字模块。 数字块可以被配置为并行地接收数据的第一组数据并存储来自另一组数据的历史比特。 SerDes发射机还可以包括在模拟电压域中工作的模拟块。 模拟块可以被配置为从数字块接收第一组数据，从数字块接收历史比特，从第一比特组生成具有一个或多个比特的比特的多个组合， 来自历史比特的更多比特，将每个比特组合对齐到多相时钟的相位; 并将每个组合输入到输出驱动器中。

公开(公告)号：US08452829B2

公开(公告)日：2013-05-28

申请号：US12144610

申请日：2008-06-23

Applicant: Dawei Huang ,  Dong J. Yoon ,  Osman Javed ,  Zuxu Qin ,  Deqiang Song ,  Daniel J. Beckman ,  Drew G. Doblar ,  Waseem Ahmad ,  Andrew Keith Joy ,  Simon Dennis Forey ,  William Franklin Leven ,  Nirmal C. Warke

Inventor： Dawei Huang ,  Dong J. Yoon ,  Osman Javed ,  Zuxu Qin ,  Deqiang Song ,  Daniel J. Beckman ,  Drew G. Doblar ,  Waseem Ahmad ,  Andrew Keith Joy ,  Simon Dennis Forey ,  William Franklin Leven ,  Nirmal C. Warke

IPC: G06F17/10

CPC classification number: H04L25/03343 ,  H04L7/0058

Abstract: A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.

Abstract translation: 定义了一个反馈模块，作为输入接收一组数据采样信号和一组参考采样信号。 通过对通过FIR滤波器发送的差分信号进行采样来生成数据和参考采样信号。 反馈模块被定义为对FIR滤波器的每个后光标操作相应的后光标计数器，并且基于所接收的数据集和参考采样信号来更新后光标计数器。 此外，反馈模块被定义为当对应于给定抽头权重的后光标计数器的大小大于或等于阈值时，产生用于FIR滤波器的给定抽头权重的抽头权重调整信号。 定义了适配模块，以将用于产生参考采样信号的参考电压调整到差分信号的状态。

公开(公告)号：US08249199B2

公开(公告)日：2012-08-21

申请号：US12342825

申请日：2008-12-23

Applicant: Drew G. Doblar ,  Dawei Huang ,  Gabriel C. Risk

Inventor： Drew G. Doblar ,  Dawei Huang ,  Gabriel C. Risk

IPC: H04L27/06

CPC classification number: H04L7/0062 ,  H04L7/0334 ,  H04L7/0337 ,  H04L7/10

Abstract: A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus includes acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjusting a recovered clock phase based on the accumulated votes. A computer readable medium storing instructions to implement a low jitter and high bandwidth CDR apparatus, the instructions includes functionality to: acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjust recovered clock phase.

Abstract translation: 实现低抖动和高带宽时钟和数据恢复（CDR）装置的方法包括获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 根据累计投票累积投票数，调整恢复时钟阶段。 一种存储用于实现低抖动和高带宽CDR装置的指令的计算机可读介质，所述指令包括以下功能：获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 累积投票并调整恢复时钟阶段。