公开(公告)号：US20100208855A1

公开(公告)日：2010-08-19

申请号：US12388223

申请日：2009-02-18

申请人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

发明人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

IPC分类号： H04L7/00

CPC分类号： H04L7/0062

摘要： A system and methods for recovering data from an input data signal are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver uses an adaptive algorithm to determine update signals for a pre-cursor tap coefficient of the FIR based on samples taken from the received data signal and conveys the update signals to the FIR. To generate update signals, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel. The phase is based on a clock recovered from the data signal. The update signals increase or decrease a pre-cursor tap coefficient setting in response to determining that the phase corresponds to a point earlier or later, respectively, than the peak amplitude of the channel's pulse response.

摘要翻译： 公开了一种从输入数据信号中恢复数据的系统和方法。 该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。 接收机使用自适应算法，基于从接收到的数据信号中取出的样本来确定FIR的前置光标抽头系数的更新信号，并将更新信号传送到FIR。 为了产生更新信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。 该相位基于从数据信号恢复的时钟。 响应于确定相位对应于分别比通道的脉冲响应的峰值幅度更早或更晚的点，更新信号增加或减少前置光标抽头系数设置。

公开(公告)号：US08218702B2

公开(公告)日：2012-07-10

申请号：US12388223

申请日：2009-02-18

申请人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

发明人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

IPC分类号： H04L7/00

CPC分类号： H04L7/0062

摘要： A system and methods for recovering data from an input data signal are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver uses an adaptive algorithm to determine update signals for a pre-cursor tap coefficient of the FIR based on samples taken from the received data signal and conveys the update signals to the FIR. To generate update signals, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel. The phase is based on a clock recovered from the data signal. The update signals increase or decrease a pre-cursor tap coefficient setting in response to determining that the phase corresponds to a point earlier or later, respectively, than the peak amplitude of the channel's pulse response.

摘要翻译： 公开了一种从输入数据信号中恢复数据的系统和方法。 该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。 接收机使用自适应算法，基于从接收到的数据信号中取出的样本来确定FIR的前置光标抽头系数的更新信号，并将更新信号传送到FIR。 为了产生更新信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。 该相位基于从数据信号恢复的时钟。 响应于确定相位对应于分别比通道的脉冲响应的峰值幅度更早或更晚的点，更新信号增加或减少前置光标抽头系数设置。

公开(公告)号：US08155214B2

公开(公告)日：2012-04-10

申请号：US12612449

申请日：2009-11-04

申请人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

发明人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

IPC分类号： H04B3/00 ,  H04L25/00

CPC分类号： H04L25/03878 ,  H04L25/03146

摘要： An asymmetric DFE receiver circuit is disclosed. The receiver circuit includes a voltage measuring unit configured to determine a signal voltage of a received signal, and a comparator unit configured to calculate a difference between the signal voltage and an evaluation threshold voltage and to compare the difference to the value of a midpoint voltage. The comparator unit is configured to generate a first control signal if the difference is greater than the midpoint voltage value or a second control signal if the signal voltage is less than the midpoint voltage value. The receiver includes an adjustment circuit configured to adjust the evaluation threshold voltage toward the signal voltage if the first control signal is generated and away from the signal voltage if the second control signal is generated. The rates of adjustment may vary depending upon whether the received signal is a transition bit or a non-transition bit.

摘要翻译： 公开了一种不对称DFE接收器电路。 接收器电路包括：电压测量单元，被配置为确定接收信号的信号电压;以及比较器单元，被配置为计算信号电压和评估阈值电压之间的差，并将该差与中点电压的值进行比较。 比较器单元被配置为如果差值大于中点电压值则产生第一控制信号，或者如果信号电压小于中点电压值则产生第二控制信号。 所述接收机包括：调整电路，被配置为如果产生所述第一控制信号并且如果产生所述第二控制信号则将所述评估阈值电压调整到所述信号电压。 调整速率可以根据接收到的信号是转换位还是非转换位而变化。

公开(公告)号：US20110103458A1

公开(公告)日：2011-05-05

申请号：US12612449

申请日：2009-11-04

申请人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

发明人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

IPC分类号： H04L27/01 ,  H04L27/00 ,  H03K5/153

CPC分类号： H04L25/03878 ,  H04L25/03146

摘要： An asymmetric DFE receiver circuit. The receiver circuit includes a voltage measuring unit configured to determine a signal voltage of a received signal, and a comparator unit configured to calculate a difference between the signal voltage and an evaluation threshold voltage and to compare the difference to the value of a midpoint voltage. The comparator unit is configured to generate a first control signal if the difference is greater than the midpoint voltage value or a second control signal if the signal voltage is less than the midpoint voltage value. The receiver includes an adjustment circuit configured to adjust the evaluation threshold voltage toward the signal voltage if the first control signal is generated and away from the signal voltage if the second control signal is generated. The rates of adjustment may vary depending upon whether the received signal is a transition bit or a non-transition bit.

摘要翻译： 不对称DFE接收器电路。 接收器电路包括：电压测量单元，被配置为确定接收信号的信号电压;以及比较器单元，被配置为计算信号电压和评估阈值电压之间的差，并将该差与中点电压的值进行比较。 比较器单元被配置为如果差值大于中点电压值则产生第一控制信号，或者如果信号电压小于中点电压值则产生第二控制信号。 所述接收机包括：调整电路，被配置为如果产生所述第一控制信号并且如果产生所述第二控制信号则将所述评估阈值电压调整到所述信号电压。 调整速率可以根据接收到的信号是转换位还是非转换位而变化。

公开(公告)号：US20110167297A1

公开(公告)日：2011-07-07

申请号：US12683147

申请日：2010-01-06

申请人： Jianghui Su ,  Deqiang Song ,  Dawei Huang ,  Muthukumar Vairavan

发明人： Jianghui Su ,  Deqiang Song ,  Dawei Huang ,  Muthukumar Vairavan

IPC分类号： G06F11/07 ,  G06F11/00

CPC分类号： H04L7/0054 ,  H04L7/0062 ,  H04L7/0334

摘要： A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.

摘要翻译： 描述接收机电路。 在接收机电路中，模数转换器（ADC）基于第一时钟信号产生数据信号的第一采样，并且时钟数据恢复（CDR）错误检测电路产生数据信号的第二采样 基于第二时钟信号。 另外，CDR错误检测电路估计来自第二样本中相邻的后续样本的第二样本中的当前样本的符号间干扰（ISI）。 基于第二样本和估计的ISI，CDR电路产生第一时钟信号和第二时钟信号，其涉及修改这些时钟信号中的一个或两者的偏差，使得当前采样与a的零交叉相关联 接收数据信号的通信信道的脉冲响应，从而减少或消除来自相邻的随后样本的ISI。

公开(公告)号：US08744024B2

公开(公告)日：2014-06-03

申请号：US13245533

申请日：2011-09-26

申请人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Osman Javed ,  Hongtao Zhang

发明人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Osman Javed ,  Hongtao Zhang

IPC分类号： H04L1/00

CPC分类号： H04L7/0054 ,  H04L7/0062

摘要： In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(−1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample.

摘要翻译： 在接收机电路中，节点接收从发射机电路传送数据的信号。 此外，接收机电路中的时钟数据恢复（CDR）电路从接收到的信号中恢复一个速率时钟信号。 CDR电路恢复时钟信号，而不会将信号的第一脉冲响应前兆相对于信号的脉冲响应光标收敛到大约零（例如，随着第一脉冲响应前兆h（-1）收敛到非零， - 零值）。 此外，第一脉冲响应前体对应于除了当前样本以外的脉冲响应的至少一个前体或后脉冲。

公开(公告)号：US20130077723A1

公开(公告)日：2013-03-28

申请号：US13245533

申请日：2011-09-26

申请人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Osman Javed ,  Hongtao Zhang

发明人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Osman Javed ,  Hongtao Zhang

IPC分类号： H04L7/02

CPC分类号： H04L7/0054 ,  H04L7/0062

摘要： In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(−1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample.

摘要翻译： 在接收机电路中，节点接收从发射机电路传送数据的信号。 此外，接收机电路中的时钟数据恢复（CDR）电路从接收到的信号中恢复一个速率时钟信号。 CDR电路恢复时钟信号，而不会将信号的第一脉冲响应前兆相对于信号的脉冲响应光标收敛到大约零（例如，随着第一脉冲响应前兆h（-1）收敛到非零， - 零值）。 此外，第一脉冲响应前体对应于除了当前样本以外的脉冲响应的至少一个前体或后脉冲。

公开(公告)号：US08181058B2

公开(公告)日：2012-05-15

申请号：US12683147

申请日：2010-01-06

申请人： Jianghui Su ,  Deqiang Song ,  Dawei Huang ,  Muthukumar Vairavan

发明人： Jianghui Su ,  Deqiang Song ,  Dawei Huang ,  Muthukumar Vairavan

IPC分类号： G06F1/04 ,  G06F13/42 ,  G06F12/00 ,  G06F11/00 ,  H03L7/00 ,  H03K5/01 ,  H03K3/017 ,  H03K7/04 ,  H03K9/00 ,  H04L12/28 ,  H04J3/06 ,  H03H7/30 ,  H04B15/00 ,  G01R13/00 ,  G01R25/00 ,  G06K5/04 ,  H03M13/00

CPC分类号： H04L7/0054 ,  H04L7/0062 ,  H04L7/0334

摘要： A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.

摘要翻译： 描述接收机电路。 在接收机电路中，模数转换器（ADC）基于第一时钟信号产生数据信号的第一采样，并且时钟数据恢复（CDR）错误检测电路产生数据信号的第二采样 基于第二时钟信号。 另外，CDR错误检测电路估计来自第二样本中相邻的后续样本的第二样本中的当前样本的符号间干扰（ISI）。 基于第二样本和估计的ISI，CDR电路产生第一时钟信号和第二时钟信号，其涉及修改这些时钟信号中的一个或两者的偏差，使得当前采样与a的零交叉相关联 接收数据信号的通信信道的脉冲响应，从而减少或消除来自相邻的随后样本的ISI。

公开(公告)号：US07844236B1

公开(公告)日：2010-11-30

申请号：US11963632

申请日：2007-12-21

申请人： Jianghui Su ,  Quang H. Trang ,  Dawei Huang

发明人： Jianghui Su ,  Quang H. Trang ,  Dawei Huang

IPC分类号： H04B7/08

CPC分类号： H04B7/0822

摘要： An apparatus and method are provided to enable an adaptation unit to be shared among a plurality of receivers. The adaptation unit provides compensation values to each receiver to enable each receiver to compensate for the pulse response effect experienced by that receiver. By sharing an adaptation unit among a plurality of receivers rather than having a dedicated adaptation unit for each receiver, the chip space needed is significantly reduced since the number of adaptation units that need to be implemented is significantly reduced. In addition, the fewer number of adaptation units leads to less power consumption during operation. Overall, the sharing of the adaptation unit enables greater efficiency and improved scalability to be achieved.

摘要翻译： 提供了一种装置和方法，以使得能够在多个接收器之间共享适配单元。 适配单元向每个接收机提供补偿值，以使得每个接收机能够补偿该接收机所经历的脉冲响应效应。 通过在多个接收机中共享适配单元而不是为每个接收机设置专用的适配单元，所需的芯片空间显着减少，因为需要实现的自适应单元的数量显着减少。 此外，适应单元的数量越少，导致运行中的功耗越来越少。 总的来说，适配单元的共享使得能够实现更高的效率和改进的可扩展性。

公开(公告)号：US20120025889A1

公开(公告)日：2012-02-02

申请号：US12848836

申请日：2010-08-02

申请人： Jianghui Su

发明人： Jianghui Su

IPC分类号： H03L5/00

CPC分类号： H04L25/0292 ,  H04L25/0272 ,  H04L25/03885

摘要： During an asymmetry testing mode of an integrated circuit, the asymmetry of an on-chip I/O circuit is tested. In particular, a transmitter circuit in the integrated circuit transmits electrical signals, which are associated with a predefined data pattern, to a receiver circuit in the integrated circuit via a communication channel (such as a differential pair of signal lines). Then the integrated circuit generates an eye pattern using the received electrical signals, and determines an asymmetry of the eye pattern about a common reference level of the received electrical signals. Furthermore, the integrated circuit performs remedial action based on the determined asymmetry. For example, the integrated circuit may compare the determined asymmetry with a predefined asymmetry criterion and, if the asymmetry exceeds the predefined asymmetry criterion, may output a result of the comparison that indicates a failure of the asymmetry test.

摘要翻译： 在集成电路的不对称测试模式期间，测试片上I / O电路的不对称性。 具体地，集成电路中的发射机电路经由通信信道（例如差分信号线对）将与预定义数据模式相关联的电信号传输到集成电路中的接收机电路。 然后，集成电路使用所接收的电信号产生眼图，并且确定眼图相对于所接收的电信号的公共参考电平的不对称性。 此外，集成电路基于所确定的不对称性来执行补救动作。 例如，集成电路可以将所确定的不对称与预定义的不对称准则进行比较，并且如果不对称超过预定义的不对称准则，则可以输出指示不对称性测试失败的比较结果。