公开(公告)号：US08125930B2

公开(公告)日：2012-02-28

申请号：US11609966

申请日：2006-12-13

申请人： Michel Ouellette ,  James Aweya ,  Delfin Y. Montuno ,  Kent Felske

发明人： Michel Ouellette ,  James Aweya ,  Delfin Y. Montuno ,  Kent Felske

IPC分类号： H04L12/28

CPC分类号： H04L41/12 ,  H04J3/0679

摘要： Algorithms and data structure are described for constructing and maintaining a clock distribution tree (“CDT”) for timing loop avoidance. The CDT algorithms and data structure allows a node to make an automated and unattended path switch to the most desirable clock source in the network. In response to a network topology change, a clock root node distributes new clock paths to all nodes in the network. In particular, the root node calculates a new clock path for each affected node by building a clock source topology tree, and identifying from that tree a path to the network node from a clock source of higher or equal stratum relative to that network node. The root node then sends a network message to each node indicating the new path that the node should use. Each node receives the message and compares the new path with the existing path. If the paths are different then the node acquires the new path just received in the message. If the paths are the same then the node does nothing and discards the message.

摘要翻译： 描述了用于构建和维护用于定时回路的时钟分布树（“CDT”）的算法和数据结构。 CDT算法和数据结构允许节点将自动和无人值守的路径切换到网络中最理想的时钟源。 响应于网络拓扑变化，时钟根节点将新的时钟路径分配给网络中的所有节点。 特别地，根节点通过构建时钟源拓扑树来计算每个受影响节点的新时钟路径，并且从该树中识别来自相对于该网络节点的较高或相等层的时钟源到网络节点的路径。 根节点然后向每个节点发送一个网络消息，指示节点应该使用的新路径。 每个节点接收消息，并将新路径与现有路径进行比较。 如果路径不同，则节点获取刚刚在消息中接收到的新路径。 如果路径相同，则节点不执行任何操作并丢弃该消息。

公开(公告)号：US07860205B1

公开(公告)日：2010-12-28

申请号：US11279410

申请日：2006-04-12

申请人： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno ,  Kent Felske

发明人： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno ,  Kent Felske

IPC分类号： H03D3/24

CPC分类号： H03L7/093 ,  H03L7/0992 ,  H03L7/0994 ,  H03L7/18 ,  H04J3/0632 ,  H04J3/0664 ,  H04N21/242 ,  H04N21/4305 ,  H04N21/64322 ,  H04N21/8547

摘要： A timestamp-based clock synchronization technique is employed for CES in packet networks. The technique is based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behavior of clock synchronization errors between a transmitter and a receiver. The technique is particularly suitable for clock synchronization in networks where the transmitter and receiver are not driven from a common timing reference but the receiver requires timing reference traceable to the transmitter clock.

摘要翻译： 基于时间戳的时钟同步技术用于分组网络中的CES。 该技术基于双指数滤波技术和线性过程模型。 线性过程模型用于描述发射机和接收机之间的时钟同步误差的行为。 该技术特别适用于发射机和接收机不从公共定时参考驱动的网络中的时钟同步，但是接收机需要可追溯到发射机时钟的定时参考。

公开(公告)号：US07643595B2

公开(公告)日：2010-01-05

申请号：US11172335

申请日：2005-06-30

申请人： James Aweya ,  Delfin Y. Montuno ,  Michel Ouellette ,  Kent Felske

发明人： James Aweya ,  Delfin Y. Montuno ,  Michel Ouellette ,  Kent Felske

IPC分类号： H04L7/00 ,  H04D3/04

CPC分类号： H03L7/0805 ,  H03D13/002 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/10 ,  H03L2207/50 ,  H04J3/0658 ,  H04J3/0664

摘要： Network elements may be synchronized over an asynchronous network by implementing a master clock as an all digital PLL that includes a Digitally Controlled Frequency Selector (DCFS), the output frequency of which may be directly controlled through the input of a control word. The PLL causes the control word input to the master DCFS to be adjusted to cause the output of the master DCFS to lock onto a reference frequency. Information associated with the control word is transmitted from the master clock to the slave clocks which are also implemented as DCFSs. By using the transmitted information to recreate the master control word, the slaves may be made to assume the same state as the master DCFS without requiring the slaves to be implemented as PLLs. The DCFS may be formed as a digitally controlled oscillator (DCO) or as a Direct Digital Synthesizer (DDS).

摘要翻译： 网络元件可以通过将主时钟实现为包括数字控制频率选择器（DCFS）的全数字PLL的主时钟同步，其输出频率可以通过控制字的输入直接控制。 PLL会导致对主DCFS的输入控制字进行调整，使主DCFS的输出锁定在参考频率上。 与控制字相关的信息从主时钟发送到也被实现为DCFS的从时钟。 通过使用所发送的信息来重建主控制字，可以使从属设备呈现与主DCFS相同的状态，而不需要将从机实现为PLL。 DCFS可以形成为数字控制振荡器（DCO）或直接数字合成器（DDS）。

公开(公告)号：US07528776B2

公开(公告)日：2009-05-05

申请号：US11689660

申请日：2007-03-22

申请人： Delfin Y. Montuno ,  James Aweya ,  Michel Ouellette ,  Kent Felske

发明人： Delfin Y. Montuno ,  James Aweya ,  Michel Ouellette ,  Kent Felske

IPC分类号： G01S3/02

CPC分类号： G01S5/06

摘要： A novel beacon-based position location technique for efficient location discovery of untethered clients in packet networks is disclosed. The position location technique utilizes the time-difference-of-arrival (“TDOA”) of a first signal transmitted by a beacon of known location and a second signal transmitted by an untethered client. The TDOA of these two signals is measured locally by at least three non-collinear signal receivers. For each of the receivers, the TDOA is used to calculate a perceived distance to the client. A circle is then calculated for each receiver, centered on the receiver and having a radius equal to the perceived distance. At least two lines defined by points of intersection of the calculated circles are then calculated. The point of intersection of the lines represents the location of the client. To facilitate operation, the signal receivers may be arranged on vertices which define a convex polygon as viewed from above. The location system requires no time (time-of-day) synchronization of the signal receivers, and only the coarse frequency synchronization, on the order of, tens of parts-per-million (ppm). The technique even works for the case where the signal receivers are run asynchronously, provided the frequency accuracies of the signal receivers are on the order of about 50 ppm or better. The technique introduces no communication overhead for the beacon, client and signal receivers. Further, the computation overhead at the signal receivers is relatively low because the location detection algorithm involves only simple algebraic operations over scalar values.

摘要翻译： 公开了一种新颖的基于信标的位置定位技术，用于在分组网络中无阻塞客户端的有效位置发现。 位置定位技术利用由已知位置的信标发送的第一信号的到达时间差（“TDOA”）和由无阻塞客户端发送的第二信号。 这两个信号的TDOA由至少三个非共线信号接收器本地测量。 对于每个接收机，TDOA用于计算到客户端的感知距离。 然后，以接收机为中心并且具有等于感知距离的半径的每个接收机计算一个圆。 然后计算由计算圆的交点定义的至少两条线。 线的交点表示客户端的位置。 为了便于操作，信号接收器可以被布置在从上方观察的限定凸多边形的顶点上。 定位系统不需要信号接收机的时间（时间）同步，只需要几十分之一百万分之几的粗略频率同步（ppm）。 该技术甚至适用于信号接收机异步运行的情况，只要信号接收机的频率精度在约50 ppm或更高的数量级。 该技术不引入信标，客户端和信号接收机的通信开销。 此外，信号接收机的计算开销相对较低，因为位置检测算法仅涉及标量值的简单代数运算。

公开(公告)号：US07047312B1

公开(公告)日：2006-05-16

申请号：US09739309

申请日：2000-12-18

申请人： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

发明人： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

IPC分类号： G06F15/16

CPC分类号： H04L47/2441 ,  H04L1/1832 ,  H04L47/10 ,  H04L47/193 ,  H04L47/25 ,  H04L47/27 ,  H04L47/29 ,  H04L47/30 ,  H04L47/35 ,  H04L69/16 ,  H04L69/163

摘要： The TCP receiver's advertised window (i.e., the receive buffer of a TCP connection) limits the maximum window and consequently the throughput that can be achieved by the sender. Thus, the idea behind TCP rate control is to match the offered network load to the available resources by modifying at an intermediate network device, the receiver's advertised window in TCP acknowledgments returning to the sources. In this disclosure, we propose a new TCP rate control scheme for a shared buffer where the buffer is logically organized into multiple queues. In the scheme, dynamic buffer thresholds are used to ensure efficient and fair usage of buffer memory among the queues. Conventional schemes allocate buffer space to each queue through the use of static buffer thresholds. This can result in unnecessary packet drops which leads to poor network performance since congested or heavily loaded queues cannot gain access to buffers not utilized by lightly loaded queues.

摘要翻译： TCP接收方的通告窗口（即TCP连接的接收缓冲区）限制了最大窗口，从而限制了发送方可以实现的吞吐量。 因此，TCP速率控制背后的想法是通过在中间网络设备修改接收者在TCP回复到源的确认窗口中，将提供的网络负载与可用资源进行匹配。 在本公开中，我们提出了一种用于共享缓冲器的新的TCP速率控制方案，其中缓冲器被逻辑地组织成多个队列。 在该方案中，使用动态缓冲器阈值来确保队列之间缓冲存储器的有效和合理使用。 传统方案通过使用静态缓冲区阈值为每个队列分配缓冲区空间。 这可能会导致不必要的数据包丢失，从而导致网络性能不佳，因为拥塞或负载较重的队列无法访问未被轻载队列使用的缓冲区。

公开(公告)号：US06901593B2

公开(公告)日：2005-05-31

申请号：US09850057

申请日：2001-05-08

申请人： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

发明人： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

IPC分类号： G06F9/00 ,  H04L12/56

CPC分类号： H04L49/90 ,  H04L47/10 ,  H04L47/12 ,  H04L47/29 ,  H04L47/32 ,  H04L49/9078

摘要： A technique for an improved active queue management scheme which dynamically changes its threshold settings as the number of connections (and system load) changes is disclosed. Using this technique, network devices can effectively control packet losses and TCP timeouts while maintaining high link utilization. The technique also allows a network to support a larger number of connections during congestion periods.

摘要翻译： 一种用于改进的主动队列管理方案的技术，其公开了连接数（和系统负载）变化的动态地改变其阈值设置。 使用这种技术，网络设备可以有效地控制分组丢失和TCP超时，同时保持较高的链路利用率。 该技术还允许网络在拥塞期间支持更大数量的连接。

公开(公告)号：US06549517B1

公开(公告)日：2003-04-15

申请号：US09209273

申请日：1998-12-11

申请人： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

发明人： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

IPC分类号： H04L1206

CPC分类号： H04L49/3081 ,  H04L2012/5635 ,  H04Q11/0478

摘要： Flow control in a network is implemented based on aggregate traffic measurements. For example, in an ATM network only the aggregate background (CBR/VBR) traffic rate and the aggregate ABR traffic rate are used, in contrast with other schemes that require per-connection rate measurements or variables. An explicit rate is calculated recursively at discrete time instances using a scaled error value which is generated in response to an aggregate ABR input rate and a desired traffic rate. Explicit rate computations can be performed entirely by software, and the interval between computations is large enough to keep the processing overhead required of the switch very low. In addition, methods consistent with the present invention achieve max-min fairness and MCR plus equal share in a natural way without any additional computation or information about bottleneck rates.

摘要翻译： 基于总流量测量实现网络中的流量控制。 例如，在ATM网络中，与使用每连接速率测量或变量的其他方案相比，仅使用聚合背景（CBR / VBR）流量速率和聚合ABR流量速率。 使用响应于总ABR输入速率和期望业务速率而产生的缩放误差值，以离散时间实例递归地计算显式速率。 显式速率计算可以完全由软件执行，并且计算之间的间隔足够大，以保持开关所需的处理开销非常低。 此外，与本发明一致的方法可以以自然的方式实现max-min公平性和MCR加上相等的份额，而无需任何额外的计算或关于瓶颈率的信息。

公开(公告)号：US08467418B2

公开(公告)日：2013-06-18

申请号：US12268008

申请日：2008-11-10

申请人： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

发明人： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

IPC分类号： H04J3/06

CPC分类号： H04L7/0079 ,  G06F1/0328 ,  H03L7/0805 ,  H03L7/085 ,  H03L7/089 ,  H03L2207/50 ,  H04J3/0632 ,  H04J3/0658

摘要： A method, system and master service interface transfer differential timing over a packet network. The transmitting service interface receives a service clock and is coupled to a receiving service interface through a network backplane. A primary reference clock is provided to time the network backplane. The primary reference clock and the service clock are used to synthesize a copy of the service clock connected to the transmitting service interface. A first control word containing an error differential between the service clock and the synthesized copy of the service clock is generated and transmitted through the network backplane via a packet. The first control word, together with the primary reference clock, is used to recreate the service clock for timing the receiving service interface.

摘要翻译： 一种方法，系统和主服务接口通过分组网络传输差分定时。 发送业务接口接收业务时钟，通过网络背板耦合到接收业务接口。 提供主参考时钟来对网络背板进行时间。 主参考时钟和服务时钟用于合成连接到发送服务接口的业务时钟的副本。 生成服务时钟和服务时钟的合成副本之间的误差的第一个控制字，并经由分组通过网络背板发送。 第一个控制字与主参考时钟一起用于重新创建用于定时接收服务接口的服务时钟。

公开(公告)号：US20120182863A1

公开(公告)日：2012-07-19

申请号：US13362319

申请日：2012-01-31

申请人： Michel Ouellette ,  James Aweya ,  Delfin Y. Montuno ,  Kent Felske ,  Michael George Mayer

发明人： Michel Ouellette ,  James Aweya ,  Delfin Y. Montuno ,  Kent Felske ,  Michael George Mayer

IPC分类号： H04L12/44 ,  H04L12/26

CPC分类号： H04L41/12 ,  H04J3/0679

摘要： In response to a network topology change, a clock root node calculates a new clock path for each affected node by building a clock source topology tree, and identifying from that tree a path to the network node from a clock source of higher or equal stratum relative to that network node. The root node then sends a network message to each node indicating the new path that the node should use. Each node receives the message and compares the new path with the existing path. If the paths are different then the node acquires the new path just received in the message. If the paths are the same then the node does nothing and discards the message.

摘要翻译： 响应于网络拓扑变化，时钟根节点通过构建时钟源拓扑树来为每个受影响的节点计算新的时钟路径，并且从该树中识别来自较高或相等层次的时钟源的网络节点的路径 到该网络节点。 根节点然后向每个节点发送一个网络消息，指示节点应该使用的新路径。 每个节点接收消息，并将新路径与现有路径进行比较。 如果路径不同，则节点获取刚刚在消息中接收到的新路径。 如果路径相同，则节点不执行任何操作并丢弃该消息。

公开(公告)号：US07656985B1

公开(公告)日：2010-02-02

申请号：US11279431

申请日：2006-04-12

申请人： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno ,  Kent Felske

发明人： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno ,  Kent Felske

IPC分类号： H03D3/24

CPC分类号： H03L7/093 ,  H03L7/0992 ,  H03L7/18 ,  H04J3/0632 ,  H04J3/0664

摘要： A timestamp-based all digital phase locked loop is utilized for clock synchronization for Circuit Emulation Service (“CES”) over packet networks. The all digital phase locked loop at a CES receiver includes a phase detector, a loop filter, a digital oscillator and a timestamp counter. The all digital phase locked loop enables the CES receiver to synchronize a local clock at the receiver with a clock at a CES transmitter, where indications of transmitter clock signals are communicated to the receiver as timestamps. The phase detector is operable to compute an error signal indicative of differences between the timestamps and a local clock signal. The loop filter is operable to reduce jitter and noise in the error signal, and thereby produce a control signal. The digital oscillator is operable to oscillate at a frequency based at least in-part on the control signal, and thereby produce a digital oscillator output signal. The timestamp counter operable to count pulses in the digital oscillator output signal, and output the local clock signal.

摘要翻译： 基于时间戳的全数字锁相环用于通过分组网络进行电路仿真服务（“CES”）的时钟同步。 CES接收机的全数字锁相环包括相位检测器，环路滤波器，数字振荡器和时间戳计数器。 全数字锁相环使得CES接收机能够使接收机处的本地时钟与CES发射机的时钟同步，其中发射机时钟信号的指示作为时间戳传送到接收机。 相位检测器可用于计算指示时间戳与本地时钟信号之间的差异的误差信号。 环路滤波器可操作以减少误差信号中的抖动和噪声，从而产生控制信号。 数字振荡器可操作以至少部分地基于控制信号以频率振荡，从而产生数字振荡器输出信号。 时间戳计数器可用于对数字振荡器输出信号中的脉冲进行计数，并输出本地时钟信号。