公开(公告)号：US07538409B2

公开(公告)日：2009-05-26

申请号：US11422690

申请日：2006-06-07

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L29/00

CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L29/7378

摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.

摘要翻译： 一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部 。 该装置还包括连接第一和第二子集电器的连通结构和形成在第二外延层的一部分中并与第二子集电器和达到通孔结构接触的N阱。 该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区，以及N +和P +扩散区之间的浅沟槽隔离结构。

公开(公告)号：US07242071B1

公开(公告)日：2007-07-10

申请号：US11382720

申请日：2006-07-06

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L29/00

CPC分类号： H01L27/0623 ,  H01L21/823892 ,  H01L27/0921

摘要： A structure comprises a deep sub-collector buried in a first epitaxial layer and a near sub-collector buried in a second epitaxial layer. The structure further comprises a deep trench isolation structure isolating a region which is substantially above the deep sub-collector, a reach-through structure in contact with the near sub-collector, and a reach-through structure in contact with the deep sub-collector to provide a low-resistance shunt, which prevents COMS latch-up of a device. The method includes forming a merged triple well double epitaxy/double sub-collector structure.

摘要翻译： 结构包括埋藏在第一外延层中的深子集电极和埋在第二外延层中的近亚集电极。 该结构还包括一个深沟槽隔离结构，该深沟槽隔离结构隔离了深层次集电极基本上方的区域，与近旁集电极接触的通孔结构以及与深子集电极接触的到达结构 以提供低电阻分流器，其防止COMS闩锁装置。 该方法包括形成合并三阱双外延/双子集电极结构。

公开(公告)号：US09087925B2

公开(公告)日：2015-07-21

申请号：US13150440

申请日：2011-06-01

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L21/84 ,  H01L21/762 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/092

CPC分类号： H01L21/84 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/8249 ,  H01L27/0635 ,  H01L27/0652 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.

摘要翻译： 半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。 集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。 该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。 器件与Si和SiGe或SiGeC区域相关联。

公开(公告)号：US08035190B2

公开(公告)日：2011-10-11

申请号：US12725792

申请日：2010-03-17

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L29/00

CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L29/7378

摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.

摘要翻译： 一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部 。 该装置还包括连接第一和第二子集电器的连通结构和形成在第二外延层的一部分中并与第二子集电器和达到通孔结构接触的N阱。 该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区，以及N +和P +扩散区之间的浅沟槽隔离结构。

公开(公告)号：US07989306B2

公开(公告)日：2011-08-02

申请号：US11770908

申请日：2007-06-29

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L21/76 ,  H01L21/322 ,  H01L21/20 ,  H01L21/36 ,  H01L23/58 ,  H01L21/02 ,  H01L29/30

CPC分类号： H01L21/84 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/8249 ,  H01L27/0635 ,  H01L27/0652 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.

摘要翻译： 半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。 集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。 该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。 器件与Si和SiGe或SiGeC区域相关联。

公开(公告)号：US20090039385A1

公开(公告)日：2009-02-12

申请号：US12237148

申请日：2008-09-24

申请人： Xuefeng LIU ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng LIU ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L29/737 ,  H01L29/00

CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L29/7378

摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.

摘要翻译： 一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部 。 该装置还包括连接第一和第二子集电器的连通结构和形成在第二外延层的一部分中并与第二子集电器和达到通孔结构接触的N阱。 该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区，以及N +和P +扩散区之间的浅沟槽隔离结构。

公开(公告)号：US20090001414A1

公开(公告)日：2009-01-01

申请号：US11770908

申请日：2007-06-29

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L21/84 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/8249 ,  H01L27/0635 ,  H01L27/0652 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.

摘要翻译： 半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。 集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。 该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。 器件与Si和SiGe或SiGeC区域相关联。

公开(公告)号：US08138579B2

公开(公告)日：2012-03-20

申请号：US11867995

申请日：2007-10-05

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L23/58

CPC分类号： H01L29/165 ,  H01L21/84 ,  H01L27/0652 ,  H01L27/1203

摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions. The invention is also directed to a design structure on which a circuit resides.

摘要翻译： 半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。 集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。 该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。 器件与Si和SiGe或SiGeC区域相关联。 本发明还涉及电路所在的设计结构。

公开(公告)号：US07718481B2

公开(公告)日：2010-05-18

申请号：US11279934

申请日：2006-04-17

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L21/8238

CPC分类号： H01L29/7322 ,  H01L27/0921 ,  H01L29/0821 ,  H01L29/66272

摘要： A structure comprises a deep subcollector buried in a first region of a dual epitaxial layer and a reachthrough structure in contact with the deep subcollector to provide a low-resistive shunt which prevents CMOS latch-up for a first device. The structure may additionally include a near subcollector formed in a higher region than the deep subcollector and under another device. At least one reachthrough electrically connects the deep subcollector and the near subcollector. The method includes forming a merged triple well double epitaxy/double subcollector.

摘要翻译： 一种结构包括埋藏在双外延层的第一区域中的深子集电极和与深子集电极接触的到达结构，以提供阻止第一器件的CMOS闩锁的低电阻分流。 该结构可以另外包括形成在比深层子集电极更高的区域内并且在另一器件下形成的近子集电极。 至少一个通孔电连接深子集电极和近子集电极。 该方法包括形成合并三阱双外延/双子集电极。

公开(公告)号：US20090001417A1

公开(公告)日：2009-01-01

申请号：US11867995

申请日：2007-10-05

申请人： Xuefeng LIU ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng LIU ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L29/24

CPC分类号： H01L29/165 ,  H01L21/84 ,  H01L27/0652 ,  H01L27/1203

摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions. The invention is also directed to a design structure on which a circuit resides.

摘要翻译： 半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。 集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。 该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。 器件与Si和SiGe或SiGeC区域相关联。 本发明还涉及电路所在的设计结构。