公开(公告)号：US20240222363A1

公开(公告)日：2024-07-04

申请号：US18605645

申请日：2024-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin PENG ,  Li-Wei CHU ,  Ming-Fu TSAI ,  Jam-Wem LEE ,  Yu-Ti SU

IPC: H01L27/02 ,  H01L23/60 ,  H01L23/62 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/747 ,  H01L29/861 ,  H01L29/87

CPC classification number: H01L27/0262 ,  H01L27/0207 ,  H01L27/0255 ,  H01L29/87 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0248 ,  H01L27/0652 ,  H01L27/0658 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/747 ,  H01L29/8611 ,  H01L2924/13034 ,  H01L2924/13035

Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

公开(公告)号：US20180006021A1

公开(公告)日：2018-01-04

申请号：US15619694

申请日：2017-06-12

Applicant: NXP B.V.

Inventor： Jozef Reinerus Maria Bergervoet ,  Gerben Willem de Jong ,  Gian Hoogzaad

IPC: H01L27/06 ,  G11C11/412 ,  H03K3/356 ,  H03K19/088

CPC classification number: H01L27/0652 ,  G11C11/412 ,  H03F1/0288 ,  H03F1/52 ,  H03F3/195 ,  H03F3/213 ,  H03F3/245 ,  H03F2200/18 ,  H03F2200/21 ,  H03F2200/411 ,  H03F2200/42 ,  H03F2200/432 ,  H03F2200/444 ,  H03F2200/451 ,  H03F2200/555 ,  H03F2200/75 ,  H03K3/356 ,  H03K3/356104 ,  H03K19/088

Abstract: A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.

公开(公告)号：US20160254373A1

公开(公告)日：2016-09-01

申请号：US15055333

申请日：2016-02-26

Applicant: D3 Semiconductor LLC

Inventor： Thomas E. Harrington, III ,  Zhijun Qu

IPC: H01L29/739 ,  H01L27/12 ,  H01L27/06 ,  H01L29/06

CPC classification number: H01L29/7395 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0652 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/8611 ,  H01L29/872

Abstract: A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device.

Abstract translation: 半导体器件包括诸如超结MOSFET，IGBT，二极管等的垂直功率器件，以及包括沿着半导体器件的顶表面具有电活性的一个或多个横向器件的表面器件。

公开(公告)号：US20060057789A1

公开(公告)日：2006-03-16

申请号：US11266259

申请日：2005-11-04

Applicant: Atsushi Kurokawa ,  Toshiaki Kitahara ,  Hiroshi Inagawa ,  Yoshinori Imamura

Inventor： Atsushi Kurokawa ,  Toshiaki Kitahara ,  Hiroshi Inagawa ,  Yoshinori Imamura

IPC: H01L21/338

CPC classification number: H01L29/66143 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0652 ,  H01L27/0658 ,  H01L27/0664 ,  H01L29/475 ,  H01L29/66212 ,  H01L29/66318 ,  H01L29/7371

Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.

公开(公告)号：US06936877B2

公开(公告)日：2005-08-30

申请号：US10101328

申请日：2002-03-19

Applicant: Mareike Katharine Klee ,  Rainer Kiewitt ,  Mike Ju ,  Wilfried Germer ,  Hans-Wolfgang Brand

Inventor： Mareike Katharine Klee ,  Rainer Kiewitt ,  Mike Ju ,  Wilfried Germer ,  Hans-Wolfgang Brand

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/108

CPC classification number: H01L28/55 ,  H01L21/31691 ,  H01L27/0629 ,  H01L27/0652 ,  H01L27/0676

Abstract: The invention relates to an electronic device provided with an electronic component which comprises an integrated circuit arrangement which has a semiconducting substrate, active components, and passive components such as capacitors with high and with low capacitance values and/or resistors. The invention further relates to a transmitter, a receiver, an electronic component, a peripheral circuit, a power supply circuit, a filter module, and an integrated circuit arrangement.

Abstract translation: 本发明涉及一种具有电子部件的电子设备，该电子部件包括集成电路装置，该集成电路装置具有半导体基板，有源部件和无源部件，例如具有高和低电容值和/或电阻器的电容器。 本发明还涉及发射机，接收机，电子部件，外围电路，电源电路，滤波器模块和集成电路装置。

公开(公告)号：US20040063292A1

公开(公告)日：2004-04-01

申请号：US10673374

申请日：2003-09-30

Applicant: Hitachi, Ltd.

Inventor： Atsushi Kurokawa ,  Toshiaki Kitahara ,  Hiroshi Inagawa ,  Yoshinori Imamura

IPC: H01L021/331

CPC classification number: H01L29/66143 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0652 ,  H01L27/0658 ,  H01L27/0664 ,  H01L29/475 ,  H01L29/66212 ,  H01L29/66318 ,  H01L29/7371

Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.

公开(公告)号：US5793097A

公开(公告)日：1998-08-11

申请号：US519096

申请日：1995-08-24

Applicant: Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

Inventor： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC: H01C7/06 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L29/00 ,  H01L23/48 ,  H01L29/76

CPC classification number: H01L27/0652 ,  H01L27/0688 ,  H01L28/20

Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

Abstract translation: 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US5240867A

公开(公告)日：1993-08-31

申请号：US757640

申请日：1991-09-11

Applicant: Kouichi Suzuki ,  Norihito Miyoshi ,  Makoto Yoshida ,  Masayuki Kokado

Inventor： Kouichi Suzuki ,  Norihito Miyoshi ,  Makoto Yoshida ,  Masayuki Kokado

IPC: H01L23/485 ,  H01L23/522 ,  H01L27/06 ,  H01L29/06

CPC classification number: H01L24/05 ,  H01L23/5221 ,  H01L24/03 ,  H01L24/06 ,  H01L27/0652 ,  H01L29/0646 ,  H01L29/0649 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: A semiconductor integrated circuit comprises a substrate of a first semiconductor type doped by a first impurity element with a first impurity density, the first semiconductor type being one of p-type and n-type semiconductors, a conductive layer formed on a back surface of the substrate, a first layer of a second semiconductor type doped by a second impurity element different from the first impurity element and formed on a front surface of the substrate, the second semiconductor type being the other of the p-type and n-type semiconductors and the first layer having a second impurity density lower than the first impurity density, a second layer of the first semiconductor type formed on the first layer for forming circuit elements therein, a first region of the second semiconductor type extending from a top surface of the first layer and reaching a top surface of the second layer, and a second region of the first semiconductor type extending from a top surface of the substrate and reaching the top surface of said second layer, the first layer and the second region forming a conductive path for supplying a power source voltage to the circuit elements in the second layer from the back surface of the substrate.

Abstract translation: 半导体集成电路包括由具有第一杂质浓度的第一杂质元素掺杂的第一半导体类型的衬底，第一半导体类型是p型和n型半导体之一，形成在第二杂质元素的背面上的导电层 衬底，由与第一杂质元素不同的第二杂质元素掺杂并形成在衬底的前表面上的第二半导体类型的第一层，第二半导体类型是p型和n型半导体中的另一个， 所述第一层具有低于所述第一杂质浓度的第二杂质密度，所述第一半导体类型的第二层形成在所述第一层上，用于在其中形成电路元件，所述第二半导体类型的第一区域从所述第一层的顶表面延伸 并且到达第二层的顶表面，并且第一半导体类型的第二区域从衬底的顶表面延伸并到达 在所述第二层的顶表面上，所述第一层和所述第二区域形成用于从所述衬底的背面向第二层中的电路元件提供电源电压的导电路径。

公开(公告)号：US4193836A

公开(公告)日：1980-03-18

申请号：US6057

申请日：1970-01-27

Applicant: Albert P. Youmans ,  David F. Allison ,  David A. Maxwell

Inventor： Albert P. Youmans ,  David F. Allison ,  David A. Maxwell

IPC: H01L21/3063 ,  H01L21/762 ,  H01L27/06 ,  H01L21/306

CPC classification number: H01L21/76297 ,  H01L21/3063 ,  H01L27/0652 ,  H01L27/0688 ,  Y10S438/928 ,  Y10S438/977

Abstract: Method for making a semiconductor structure having isolated islands of semiconductor material from a semiconductor body by forming a first layer of insulating material on a surface of the body having a first support structure upon the layer of insulating material and then forming grooves in the semiconductor body which extend to the layer of insulating material formed from the semiconductor body. A second layer of insulating material is then formed on the exposed surfaces of the islands. A second support structure is then formed on the second layer of insulating material. Thereafter, the first support structure is removed and circuit devices are fabricated in the isolated islands.

Abstract translation: 通过在绝缘材料层上形成具有第一支撑结构的本体的表面上形成第一绝缘材料层，然后在半导体本体中形成凹槽来制造具有半导体本体的隔离岛状半导体材料的半导体结构的方法， 延伸到由半导体本体形成的绝缘材料层。 然后在岛的暴露表面上形成第二层绝缘材料。 然后在第二绝缘材料层上形成第二支撑结构。 此后，去除第一支撑结构并且在隔离的岛中制造电路装置。

公开(公告)号：US3967310A

公开(公告)日：1976-06-29

申请号：US420590

申请日：1973-11-30

Applicant: Masatada Horiuchi ,  Takashi Tokuyama ,  Takao Miyazaki

Inventor： Masatada Horiuchi ,  Takashi Tokuyama ,  Takao Miyazaki

IPC: H01L21/00 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/82 ,  H01L23/29 ,  H01L23/532 ,  H01L27/06 ,  H01L29/00 ,  H01L29/51 ,  H01L27/04 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/513 ,  H01L21/00 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/82 ,  H01L23/29 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/0652 ,  H01L29/00 ,  H01L29/51 ,  H01L2924/0002

Abstract: After desired impurities are diffused into a semiconductor substrate through a masking layer of SiO.sub.2 formed thereupon so as to form a semiconductor device, the masking layer is completely removed therefrom and thereafter more than two thin layers of different insulating materials are deposited upon the cleaned surface of the semiconductor device thus providing a method of forming a semiconductor device with an improved passivation film thereon. Said insulating materials are selected from the group consisting of silicon dioxide, a silicon nitride, alumina, boro-silicate glass, phospho-silicate glass, alumino-silicate glass, alumino-phospho-silicate glass and alumino-boro-silicate glass, and the thickness of each thin layer is in the range of 300 to 1500 angstroms and the first layer is silicon dioxide.

Abstract translation: 在所需的杂质通过其上形成的SiO 2掩蔽层扩散到半导体衬底中以形成半导体器件之后，完全去除掩模层，然后将不止于两层不同绝缘材料的不同绝缘材料沉积在清洁表面上 因此，半导体器件提供了在其上形成具有改进的钝化膜的半导体器件的方法。 所述绝缘材料选自二氧化硅，氮化硅，氧化铝，硼硅酸盐玻璃，磷硅酸盐玻璃，铝硅酸盐玻璃，铝磷酸硅酸盐玻璃和铝 - 硼硅酸盐玻璃，以及 每个薄层的厚度在300至1500埃的范围内，第一层是二氧化硅。