Quantum efficiency enhancement for CMOS Imaging sensor with borderless contact
    11.
    发明申请
    Quantum efficiency enhancement for CMOS Imaging sensor with borderless contact 有权
    CMOS无损触摸传感器的量子效率提升

    公开(公告)号:US20060148119A1

    公开(公告)日:2006-07-06

    申请号:US11360750

    申请日:2006-02-23

    IPC分类号: H01L21/00

    摘要: The present invention is CMOS image sensor and its method of fabrication. This invention provides an efficient structure to improve the quantum efficiency of a CMOS type photodiode with borderless contact. The image sensor comprises a N-well/P-substrate type photodiode with borderless contact and dielectric structure covering the photodiode region. The dielectric structure is located between the photodiode and the interlevel dielectric (ILD) and is used as a buffer layer for the borderless contact. The method of fabricating a high performance photodiode comprises forming a photodiode in the n-well region of a shallow trench, and embedding a dielectric material between the ILD oxide and the photodiode having a refraction index higher than the ILD oxide.

    摘要翻译: 本发明是CMOS图像传感器及其制造方法。 本发明提供了一种提高具有无边界接触的CMOS型光电二极管的量子效率的有效结构。 图像传感器包括覆盖光电二极管区域的无接触接触和介电结构的N阱/ P基板型光电二极管。 电介质结构位于光电二极管和层间电介质(ILD)之间,用作无边界接触的缓冲层。 制造高性能光电二极管的方法包括在浅沟槽的n阱区域中形成光电二极管,并且在ILD氧化物和具有高于ILD氧化物的折射率的光电二极管之间嵌入电介质材料。

    Lateral P-I-N photodiode element with high quantum efficiency for a CMOS image sensor
    12.
    发明授权
    Lateral P-I-N photodiode element with high quantum efficiency for a CMOS image sensor 有权
    用于CMOS图像传感器的具有高量子效率的横向P-I-N光电二极管元件

    公开(公告)号:US06323054B1

    公开(公告)日:2001-11-27

    申请号:US09583398

    申请日:2000-05-31

    IPC分类号: H01L2100

    CPC分类号: H01L27/14609

    摘要: A process for fabricating a lateral photodiode element, for an image sensor cell, with an increased depletion region, has been developed. The process features protecting a portion of the semiconductor substrate from ion implantation procedures used to create the P well, and the N well components of the lateral photodiode element. The protected region, or the space between the P well and N well regions, allows a larger depletion region to be realized, when compared to lateral photodiode elements in which the N well and P well regions butt. The space between the P well and N well regions, between about 0.2 to 0.4 um, result in the desired P well—intrinsic or P type semiconductor substrate—N well, (P-I-N), lateral photodiode element.

    摘要翻译: 已经开发了用于图像传感器单元的具有增加的耗尽区域的横向光电二极管元件的制造方法。 该工艺特征是保护半导体衬底的一部分免受用于产生P阱的离子注入工艺和横向光电二极管元件的N阱部件。 与N阱和P阱区对接的横向光电二极管元件相比,受保护区域或P阱和N阱区域之间的空间允许实现更大的耗尽区域。 在P阱和N阱区之间的间隔在约0.2至0.4μm之间,导致所需的P本征或P型半导体衬底N阱(P-I-N),横向光电二极管元件。

    Technology for high performance buried contact and tungsten polycide
gate integration
    13.
    发明授权
    Technology for high performance buried contact and tungsten polycide gate integration 失效
    技术用于高性能埋地接触和钨硅化合物门集成

    公开(公告)号:US5998269A

    公开(公告)日:1999-12-07

    申请号:US35139

    申请日:1998-03-05

    摘要: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

    摘要翻译: 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉,其中它们不被掩模覆盖以形成多晶硅栅电极和互连线,其中间隙留在栅电极和互连线之间。 介电材料层沉积在半导体衬底上以填补间隙。 去除硬掩模层。 多晶硅层被蚀刻掉,其未被掩埋的接触掩模覆盖,以形成到半导体衬底的开口。 植入离子以形成埋入的接触。 沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。 去除介电材料层。 沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物,以在集成电路的制造中完成掩埋接触结的形成。

    Semiconductor device having enhanced photo sensitivity and method for manufacture thereof
    14.
    发明授权
    Semiconductor device having enhanced photo sensitivity and method for manufacture thereof 有权
    具有增强的光敏度的半导体器件及其制造方法

    公开(公告)号:US08124495B2

    公开(公告)日:2012-02-28

    申请号:US11627883

    申请日:2007-01-26

    IPC分类号: H01L21/76

    CPC分类号: H01L27/14689 H01L27/1463

    摘要: Provided are a semiconductor device and a method for its manufacture. In one example, the method includes forming an isolation structure having a first refraction index over a sensor embedded in a substrate. A first layer having a second refraction index that is different from the first refraction index is formed over the isolation structure. The first layer is removed from at least a portion of the isolation structure. A second layer having a third refraction index is formed over the isolation structure after the first layer is removed. The third refraction index is substantially similar to the first refraction index.

    摘要翻译: 提供半导体器件及其制造方法。 在一个示例中,该方法包括在嵌入基板中的传感器上形成具有第一折射率的隔离结构。 在隔离结构上形成具有与第一折射率不同的第二折射率的第一层。 从隔离结构的至少一部分去除第一层。 在去除第一层之后,在隔离结构上形成具有第三折射率的第二层。 第三折射率基本上类似于第一折射率。

    Color filter for image sensor
    15.
    发明授权
    Color filter for image sensor 有权
    图像传感器滤色片

    公开(公告)号:US08054371B2

    公开(公告)日:2011-11-08

    申请号:US11676388

    申请日:2007-02-19

    CPC分类号: G02B5/201 G02B5/223

    摘要: An image sensor device includes a semiconductor substrate having a front surface and a back surface, pixels formed on the front surface of the semiconductor substrate, and grid arrays aligned with one of the pixels. One of the grid arrays is configured to allow a wavelength of light to pass through to the corresponding one of the pixels. The grid arrays are disposed overlying the front or back surface of the semiconductor substrate.

    摘要翻译: 图像传感器装置包括具有前表面和后表面的半导体衬底,形成在半导体衬底的前表面上的像素和与像素之一对准的栅格阵列。 网格阵列中的一个被配置为允许光的波长通过到相应的一个像素。 栅格阵列设置在半导体衬底的前表面或后表面上。

    Alignment for backside illumination sensor
    16.
    发明授权
    Alignment for backside illumination sensor 有权
    背面照明传感器对准

    公开(公告)号:US07588993B2

    公开(公告)日:2009-09-15

    申请号:US11951916

    申请日:2007-12-06

    IPC分类号: H01L21/76

    摘要: An apparatus and manufacturing method thereof, wherein an integrated circuit is located in a first region of a substrate having first and second opposing major surfaces, and wherein an alignment mark is located in a second region of the substrate and extends through the substrate between the first and second surfaces. The alignment mark may protrude from the first and/or second surfaces, and/or may comprise a plurality of substantially similar alignment marks. The second region may interpose the first region and a perimeter of the substrate. The second region may comprise a scribe region.

    摘要翻译: 一种装置及其制造方法,其中集成电路位于具有第一和第二相对主表面的基板的第一区域中,并且其中对准标记位于所述基板的第二区域中,并且延伸穿过所述基板在所述第一 和第二表面。 对准标记可以从第一和/或第二表面突出,和/或可以包括多个基本相似的对准标记。 第二区域可以插入衬底的第一区域和周边。 第二区域可以包括划线区域。

    CMOS image sensor
    17.
    发明授权
    CMOS image sensor 有权
    CMOS图像传感器

    公开(公告)号:US07253458B2

    公开(公告)日:2007-08-07

    申请号:US10980959

    申请日:2004-11-04

    IPC分类号: H01L27/148

    摘要: A complementary metal oxide semiconductor field effect transistor (CMOS-FET) image sensor. An active photosensing pixel is formed on a substrate. At least one side of the pixel has a width equal to or less than approximately 3 μm. At least one dielectric layer is disposed on the substrate covering the pixel. A color filter is disposed on the least one dielectric layer. A microlens array is disposed on the color filter of the pixel, and the sum of the thickness of all dielectric layers and the color filter divided by the pixel width is equal to or less than approximately 1.87.

    摘要翻译: 互补金属氧化物半导体场效应晶体管(CMOS-FET)图像传感器。 在基板上形成有源感光像素。 像素的至少一侧具有等于或小于约3μm的宽度。 在覆盖像素的基板上设置至少一个电介质层。 滤色器设置在至少一个电介质层上。 微透镜阵列设置在像素的滤色器上,所有电介质层和滤色器的厚度之和除以像素宽度等于或小于约1.87。

    Asymmetrical reset transistor with double-diffused source for CMOS image sensor
    20.
    发明授权
    Asymmetrical reset transistor with double-diffused source for CMOS image sensor 有权
    CMOS图像传感器双扩散源非对称复位晶体管

    公开(公告)号:US06642076B1

    公开(公告)日:2003-11-04

    申请号:US10278134

    申请日:2002-10-22

    IPC分类号: H01L2100

    摘要: A new method to form CMOS image sensors in the manufacture of an integrated circuit device is achieved. The method comprises providing a semiconductor substrate. Sensor diodes are formed in the semiconductor substrate each comprising a first terminal and a second terminal. Gates are formed for transistors in the CMOS image sensors. The gates comprise a conductor layer overlying the semiconductor substrate with an insulating layer therebetween. The transistors include reset transistors. Ions are implanted into the semiconductor substrate to form source/drain regions for the transistors. The source regions of the reset transistors are formed in the first terminals of the sensor diodes. Ions are implanted into the reset transistor sources to form double diffused sources. The implanting is blocked from other source/drain regions.

    摘要翻译: 实现了在制造集成电路器件中形成CMOS图像传感器的新方法。 该方法包括提供半导体衬底。 传感器二极管形成在每个包括第一端子和第二端子的半导体衬底中。 为CMOS图像传感器中的晶体管形成栅极。 栅极包括覆盖半导体衬底的导体层,其间具有绝缘层。 晶体管包括复位晶体管。 将离子注入到半导体衬底中以形成用于晶体管的源极/漏极区域。 复位晶体管的源极区域形成在传感器二极管的第一端子中。 离子被植入到复位晶体管源中以形成双扩散源。 植入物从其它源极/漏极区域被阻挡。