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公开(公告)号：US20100252801A1
公开(公告)日：2010-10-07
申请号：US12417819
申请日：2009-04-03
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/517 , H01L29/66439 , H01L29/7843 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.
摘要翻译： 将两端具有两个半导体焊盘的半导体纳米线悬置在衬底上。 在半导体衬底的两个半导体衬底上形成有应力产生衬垫部分，同时露出半导体纳米线的中间部分。 在半导体纳米线的中间部分形成栅极电介质和栅电极，同时半导体纳米线由于应力产生衬垫部分而处于纵向应力之下。 由于栅极电介质和栅电极的形成锁定在半导体纳米线的应变状态，半导体纳米线的中间部分在移除应力产生衬里之后处于内置的固有纵向应力。 源极和漏极区域形成在半导体焊盘中以提供半导体纳米线晶体管。 中间线（MOL）电介质层可以直接形成在源极和漏极焊盘上。
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公开(公告)号：US20100252800A1
公开(公告)日：2010-10-07
申请号：US12417808
申请日：2009-04-03
IPC分类号： H01L29/66 , H01L21/20 , H01L27/092 , H01L21/8238
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/84 , H01L27/092 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/7843 , H01L29/78696 , Y10S977/762 , Y10S977/938 , Y10S977/957
摘要： A p-type semiconductor nanowire transistor is formed on the first semiconductor nanowire and an n-type semiconductor nanowire transistor is formed on the second semiconductor nanowire. The first and second semiconductor nanowires have a rectangular cross-sectional area with different width-to-height ratios. The type of semiconductor nanowires for each semiconductor nanowire transistor is selected such that top and bottom surfaces provide a greater on-current per unit width than sidewall surfaces in a semiconductor nanowire having a greater width-to-height ratio, while sidewall surfaces provide a greater on-current per unit width than top and bottom surfaces in the other semiconductor nanowire having a lesser width-to-height ratio. Different types of stress-generating material layers may be formed on the first and second semiconductor nanowire transistors to provide opposite types of stress, which may be employed to enhance the on-current of the first and second semiconductor nanowire transistors.
摘要翻译： 在第一半导体纳米线上形成p型半导体纳米线晶体管，在第二半导体纳米线上形成n型半导体纳米线晶体管。 第一和第二半导体纳米线具有具有不同宽度与高度比的矩形横截面面积。 选择每个半导体纳米线晶体管的半导体纳米线的类型，使得顶表面和底表面在具有更大宽度与高度比的半导体纳米线中提供比单元宽度更大的导通电流，而侧壁表面提供更大的 具有比宽度与高度比较小的另一半导体纳米线中的顶表面和底表面的每单位宽度的电流。 可以在第一和第二半导体纳米线晶体管上形成不同类型的应力产生材料层以提供相反类型的应力，这可以用于增强第一和第二半导体纳米线晶体管的导通电流。
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公开(公告)号：US08299565B2
公开(公告)日：2012-10-30
申请号：US13075551
申请日：2011-03-30
IPC分类号： H01L29/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , H01L29/0673 , H01L29/125 , H01L29/42392 , H01L29/78696
摘要： Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning.
摘要翻译： 通过在电介质材料层上的半导体层进行平版印刷图案，形成各自包括半导体连接部分和两个邻接焊盘部分的原型半导体结构。 半导体连接部分的侧壁被定向为使第一类型半导体结构的空穴迁移率最大化，并使第二类型半导体结构的电子迁移率最大化。 通过半导体结构的氧化来减薄半导体连接部分的宽度，以不同的速率降低不同的晶体取向。 半导体连接部分的宽度是预定的，使得在半导体连接部分的侧壁上的不同量的薄化导致在变薄后得到的半导体纳米线的目标亚光刻尺寸。 通过补偿不同晶面的不同稀释速率，可以为不同的晶体取向形成具有最佳亚光刻宽度的半导体纳米线，而不会过度稀化或不充分变薄。
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公开(公告)号：US08013324B2
公开(公告)日：2011-09-06
申请号：US12417815
申请日：2009-04-03
IPC分类号： H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/76838 , H01L29/0673 , H01L29/068 , H01L29/125 , H01L29/42392 , H01L29/78696 , H01L2221/1094
摘要： In one embodiment, a semiconductor nanowire having a monotonically increasing width with distance from a middle portion toward adjoining semiconductor pads is provided. A semiconductor link portion having tapered end portions is lithographically patterned. During the thinning process that forms a semiconductor nanowire, the taper at the end portions of the semiconductor nanowire provides enhanced mechanical strength to prevent structural buckling or bending. In another embodiment, a semiconductor nanowire having bulge portions are formed by preventing the thinning of a semiconductor link portion at pre-selected positions. The bulge portions having a greater width than a middle portion of the semiconductor nanowire provides enhanced mechanical strength during thinning of the semiconductor link portion so that structural damage to the semiconductor nanowire is avoided during thinning.
摘要翻译： 在一个实施例中，提供了具有从中间部分到相邻半导体焊盘的距离的单调增加的宽度的半导体纳米线。 具有锥形端部的半导体连接部分被光刻图案化。 在形成半导体纳米线的薄化工艺期间，半导体纳米线端部的锥度提供增强的机械强度以防止结构弯曲或弯曲。 在另一个实施例中，通过防止半导体连接部分在预先选定位置的变薄而形成具有凸出部分的半导体纳米线。 具有比半导体纳米线的中间部分更大的宽度的凸起部分在半导体连接部分的薄化期间提供增强的机械强度，使得在减薄期间避免对半导体纳米线的结构损坏。
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公开(公告)号：US20100252814A1
公开(公告)日：2010-10-07
申请号：US12417796
申请日：2009-04-03
IPC分类号： H01L29/12 , H01L21/782
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , H01L29/0673 , H01L29/125 , H01L29/42392 , H01L29/78696
摘要： Prototype semiconductor structures each including a semiconductor link portion and two adjoined pad portions are formed by lithographic patterning of a semiconductor layer on a dielectric material layer. The sidewalls of the semiconductor link portions are oriented to maximize hole mobility for a first-type semiconductor structures, and to maximize electron mobility for a second-type semiconductor structures. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link portions at different rates for different crystallographic orientations. The widths of the semiconductor link portions are predetermined so that the different amount of thinning on the sidewalls of the semiconductor link portions result in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed for different crystallographic orientations without excessive thinning or insufficient thinning.
摘要翻译： 通过在电介质材料层上的半导体层进行平版印刷图案，形成各自包括半导体连接部分和两个邻接焊盘部分的原型半导体结构。 半导体连接部分的侧壁被定向为使第一类型半导体结构的空穴迁移率最大化，并使第二类型半导体结构的电子迁移率最大化。 通过半导体结构的氧化来减薄半导体连接部分的宽度，以不同的速率降低不同的晶体取向。 半导体连接部分的宽度是预定的，使得在半导体连接部分的侧壁上的不同量的薄化导致在变薄后得到的半导体纳米线的目标亚光刻尺寸。 通过补偿不同晶面的不同稀释速率，可以为不同的晶体取向形成具有最佳亚光刻宽度的半导体纳米线，而不会过度稀化或不充分变薄。
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公开(公告)号：US08232165B2
公开(公告)日：2012-07-31
申请号：US13184004
申请日：2011-07-15
IPC分类号： H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/42392 , H01L29/6675 , H01L29/78687 , H01L29/78696 , Y10S977/762 , Y10S977/814 , Y10S977/825 , Y10S977/932 , Y10S977/936 , Y10S977/937 , Y10S977/938
摘要： A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.
摘要翻译： 半导体结构包括n沟道场效应晶体管（NFET）纳米线，所述NFET纳米线包括围绕NFET纳米线的核缠绕的膜，所述膜包覆被配置为在NFET纳米线中提供拉伸应力。 制造半导体结构的方法包括生长围绕半导体结构的n沟道场效应晶体管（NFET）纳米线的芯缠绕的膜，膜缠绕被配置为在NFET纳米线中提供拉伸应力。
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公开(公告)号：US20110275198A1
公开(公告)日：2011-11-10
申请号：US13184004
申请日：2011-07-15
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/42392 , H01L29/6675 , H01L29/78687 , H01L29/78696 , Y10S977/762 , Y10S977/814 , Y10S977/825 , Y10S977/932 , Y10S977/936 , Y10S977/937 , Y10S977/938
摘要： A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.
摘要翻译： 半导体结构包括n沟道场效应晶体管（NFET）纳米线，所述NFET纳米线包括围绕NFET纳米线的芯缠绕的膜，所述膜包覆被配置为在NFET纳米线中提供拉伸应力。 制造半导体结构的方法包括生长围绕半导体结构的n沟道场效应晶体管（NFET）纳米线的芯缠绕的膜，膜缠绕被配置为在NFET纳米线中提供拉伸应力。
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公开(公告)号：US20110104860A1
公开(公告)日：2011-05-05
申请号：US13004340
申请日：2011-01-11
IPC分类号： H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/517 , H01L29/66439 , H01L29/7843 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.
摘要翻译： 将两端具有两个半导体焊盘的半导体纳米线悬置在衬底上。 在半导体衬底的两个半导体衬底上形成有应力产生衬垫部分，同时露出半导体纳米线的中间部分。 在半导体纳米线的中间部分形成栅极电介质和栅电极，同时半导体纳米线由于应力产生衬垫部分而处于纵向应力之下。 由于栅极电介质和栅电极的形成锁定在半导体纳米线的应变状态，半导体纳米线的中间部分在移除应力产生衬里之后处于内置的固有纵向应力。 源极和漏极区域形成在半导体焊盘中以提供半导体纳米线晶体管。 中间线（MOL）电介质层可以直接形成在源极和漏极焊盘上。
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公开(公告)号：US07902541B2
公开(公告)日：2011-03-08
申请号：US12417819
申请日：2009-04-03
IPC分类号： H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/517 , H01L29/66439 , H01L29/7843 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.
摘要翻译： 将两端具有两个半导体焊盘的半导体纳米线悬置在衬底上。 在半导体衬底的两个半导体衬底上形成有应力产生衬垫部分，同时露出半导体纳米线的中间部分。 在半导体纳米线的中间部分形成栅极电介质和栅电极，同时半导体纳米线由于应力产生衬垫部分而处于纵向应力之下。 由于栅极电介质和栅电极的形成锁定在半导体纳米线的应变状态，半导体纳米线的中间部分在移除应力产生衬里之后处于内置的固有纵向应力。 源极和漏极区域形成在半导体焊盘中以提供半导体纳米线晶体管。 中间线（MOL）电介质层可以直接形成在源极和漏极焊盘上。
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公开(公告)号：US20110049473A1
公开(公告)日：2011-03-03
申请号：US12549741
申请日：2009-08-28
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/42392 , H01L29/6675 , H01L29/78687 , H01L29/78696 , Y10S977/762 , Y10S977/814 , Y10S977/825 , Y10S977/932 , Y10S977/936 , Y10S977/937 , Y10S977/938
摘要： A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.
摘要翻译： 半导体结构包括n沟道场效应晶体管（NFET）纳米线，所述NFET纳米线包括围绕NFET纳米线的芯缠绕的膜，所述膜包覆被配置为在NFET纳米线中提供拉伸应力。 制造半导体结构的方法包括生长围绕半导体结构的n沟道场效应晶体管（NFET）纳米线的芯缠绕的膜，膜缠绕被配置为在NFET纳米线中提供拉伸应力。
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