公开(公告)号：US20180358265A1

公开(公告)日：2018-12-13

申请号：US16036118

申请日：2018-07-16

Applicant: International Business Machines Corporation

Inventor： Qing Cao ,  Oki Gunawan

IPC: H01L21/768 ,  H01L21/283 ,  H01L21/66 ,  H01L21/02 ,  H01F7/02 ,  H01L23/532 ,  H01L43/12 ,  B82Y40/00 ,  G01D5/24 ,  H01F7/00 ,  H01F7/20

CPC classification number: H01L21/76897 ,  B82Y40/00 ,  F16C32/0423 ,  F16C32/0478 ,  G01D5/24 ,  H01F7/00 ,  H01F7/02 ,  H01F7/0236 ,  H01F7/0247 ,  H01F7/0273 ,  H01F7/0284 ,  H01F7/202 ,  H01L21/02697 ,  H01L21/283 ,  H01L21/76838 ,  H01L21/76892 ,  H01L22/10 ,  H01L23/53276 ,  H01L43/12 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/762 ,  H01L2924/00

Abstract: A magnetic trap is configured to arrange at least one diamagnetic rod. The magnetic trap includes first and second magnets on a substrate that forms the magnetic trap defining a template configured to self-assemble diamagnetic material. Each of the first and second magnets extends along a longitudinal direction to define a magnet length, and contact each other to define a contact line. The first magnet and the second magnet have a diametric magnetization in a direction perpendicular to the contact line and the longitudinal direction so as to generate a longitudinal energy potential that traps the diamagnetic rod along the longitudinal direction.

公开(公告)号：US20180323399A1

公开(公告)日：2018-11-08

申请号：US16015015

申请日：2018-06-21

Applicant: Duksan Hi-Metal Co., Ltd.

Inventor： Young Zo YOO ,  Yoon Soo CHOI ,  Yeong Jin LIM

IPC: H01L51/52 ,  B82Y40/00

CPC classification number: H01L51/5206 ,  B82Y20/00 ,  B82Y30/00 ,  B82Y40/00 ,  Y10S977/762 ,  Y10S977/766 ,  Y10S977/81 ,  Y10S977/892 ,  Y10S977/896 ,  Y10S977/932

Abstract: A metal nanowire according to an embodiment of the invention includes at least one bent portion. An angle (α) between an n-th wire portion and an (n+1)-th wire portion connected to the n-th wire portion through an n-th bent portion satisfies an inequation of 0°

公开(公告)号：US20180315947A1

公开(公告)日：2018-11-01

申请号：US16014876

申请日：2018-06-21

Applicant: DUKSAN HI-METAL CO., LTD

Inventor： Young Zo YOO ,  Yoon Soo CHOI ,  Yeong Jin LIM

IPC: H01L51/52 ,  B82Y30/00 ,  B82Y40/00 ,  B82Y20/00

CPC classification number: H01L51/5206 ,  B82Y20/00 ,  B82Y30/00 ,  B82Y40/00 ,  Y10S977/762 ,  Y10S977/766 ,  Y10S977/81 ,  Y10S977/892 ,  Y10S977/896 ,  Y10S977/932

Abstract: A metal nanowire according to an embodiment of the invention includes at least one bent portion. An angle (α) between an n-th wire portion and an (n+1)-th wire portion connected to the n-th wire portion through an n-th bent portion satisfies an inequation of 0°

公开(公告)号：US20180294795A1

公开(公告)日：2018-10-11

申请号：US15949794

申请日：2018-04-10

Applicant: Regents of the University of Minnesota

Inventor： Jeong-Hyun Cho ,  Chao Liu

IPC: H03H9/24 ,  H03H3/00

CPC classification number: B82B3/0014 ,  B82B1/001 ,  B82Y15/00 ,  H01P7/082 ,  H01P7/10 ,  H03H3/00 ,  H03H9/24 ,  Y10S977/762 ,  Y10S977/81 ,  Y10S977/888 ,  Y10S977/932

Abstract: Nanopillar-based closed ring resonator (CRR) MMs, utilizing displacement current in the nano gap medium between nanopillars that significantly increases energy storage in the MMs, leading to an enhanced Q-factor of at least 11000. A metallic nanopillar array is designed in the form of a closed ring (e.g., square-shape) CRR

公开(公告)号：US10038054B2

公开(公告)日：2018-07-31

申请号：US15429126

申请日：2017-02-09

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Seung Hoon Sung

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L21/306

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  Y10S977/762 ,  Y10S977/89 ,  Y10S977/938

Abstract: Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

公开(公告)号：US10020371B2

公开(公告)日：2018-07-10

申请号：US15252125

申请日：2016-08-30

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Willy Rachmady ,  Van H. Le ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Han Wui Then ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L23/485 ,  H01L29/66 ,  H01L29/775 ,  G11C7/02 ,  H01L23/535 ,  H01L27/115 ,  H01L29/16 ,  H01L29/78 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L29/41791 ,  B82Y40/00 ,  B82Y99/00 ,  G11C7/02 ,  H01L23/485 ,  H01L23/535 ,  H01L27/115 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  H01L2924/0002 ,  Y10S977/762 ,  Y10S977/89 ,  H01L2924/00

Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

公开(公告)号：US10008566B2

公开(公告)日：2018-06-26

申请号：US14025041

申请日：2013-09-12

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/06 ,  H01L21/8234 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823487 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  Y10S977/762 ,  Y10S977/938

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a first distance from a first portion of the first type region. The semiconductor device includes a gate region surrounding the channel region. A first portion of the gate region is separated a second distance from the first portion of the first type region. The second distance is greater than the first distance.

公开(公告)号：US09991342B2

公开(公告)日：2018-06-05

申请号：US14438497

申请日：2013-10-25

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  ALEDIA

Inventor： Bérangère Hyot ,  Benoit Amstatt ,  Marie-Françoise Armand ,  Florian Dupont

IPC: H01L29/06 ,  H01L21/02 ,  H01L33/04 ,  B82Y10/00 ,  B82Y40/00 ,  C30B25/00 ,  C30B25/18 ,  C30B29/16 ,  C30B29/36 ,  C30B29/40 ,  C30B29/60 ,  H01L29/40 ,  H01L29/66 ,  H01L29/41 ,  H01L33/16 ,  H01L33/12 ,  B82Y99/00 ,  H01L33/24

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  C30B25/005 ,  C30B25/183 ,  C30B29/16 ,  C30B29/36 ,  C30B29/40 ,  C30B29/406 ,  C30B29/605 ,  H01L21/02104 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02603 ,  H01L21/0262 ,  H01L29/401 ,  H01L29/413 ,  H01L29/6609 ,  H01L33/04 ,  H01L33/12 ,  H01L33/16 ,  H01L33/24 ,  Y10S977/762 ,  Y10S977/84 ,  Y10S977/932

Abstract: The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said nanowire (2). The buffer layer (3) is at least partly formed by a transition metal nitride layer (9) from which extends the nanowire (2), said transition metal nitride being chosen from: vanadium nitride, chromium nitride, zirconium nitride, niobium nitride, molybdenum nitride, hafnium nitride or tantalum nitride.

公开(公告)号：US09968438B2

公开(公告)日：2018-05-15

申请号：US14935395

申请日：2015-11-07

Applicant: International Business Machines Corporation

Inventor： Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01C17/08 ,  A61F2/10 ,  H01L29/06 ,  H01L29/16 ,  H01L27/12 ,  A61F2/50 ,  H01L21/3213 ,  A61F2/76 ,  H01L23/498 ,  G01L5/22 ,  A61F2/70 ,  A61F2/68 ,  B82Y15/00

CPC classification number: A61F2/105 ,  A61F2/50 ,  A61F2/5044 ,  A61F2/70 ,  A61F2/76 ,  A61F2002/5001 ,  A61F2002/5007 ,  A61F2002/5061 ,  A61F2002/6827 ,  A61F2002/7635 ,  B82Y15/00 ,  G01L5/228 ,  H01L21/32133 ,  H01L23/4985 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/0676 ,  H01L29/16 ,  Y10S977/762 ,  Y10S977/925 ,  Y10T29/49103

Abstract: High resolution active matrix nanowire circuits enable a flexible platform for artificial electronic skin having pressure sensing capability. Comb-like interdigitated nanostructures extending vertically from a pair of opposing, flexible assemblies facilitate pressure sensing via changes in resistance caused by varying the extent of contact among the interdigitated nanostructures. Electrically isolated arrays of vertically extending, electrically conductive nanowires or nanofins are formed from a doped, electrically conductive layer, each of the arrays being electrically connected to a transistor in an array of transistors. The nanowires or nanofins are interdigitated with further electrically conductive nanowires or nanofins mounted to a flexible handle.

公开(公告)号：US09947829B2

公开(公告)日：2018-04-17

申请号：US13805273

申请日：2011-06-27

Applicant: Jonas Ohlsson

Inventor： Jonas Ohlsson

IPC: H01L33/12 ,  B82Y10/00 ,  H01L29/06 ,  H01L33/18 ,  H01L21/02 ,  B82Y20/00 ,  B82Y40/00 ,  H01L33/00 ,  H01L33/06 ,  H01L33/08 ,  H01L33/24 ,  B82Y99/00

CPC classification number: H01L33/12 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02444 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02603 ,  H01L29/0665 ,  H01L29/0676 ,  H01L29/0684 ,  H01L33/007 ,  H01L33/06 ,  H01L33/08 ,  H01L33/18 ,  H01L33/24 ,  Y10S977/762

Abstract: The present invention provides a substrate (1) with a bulk layer (3) and a buffer layer (4) having a thickness of less than 2 μm arranged on the bulk layer (3) for growth of a multitude of nanowires (2) oriented in the same direction on a surface (5) of the buffer layer (4). A nanowire structure, a nanowire light emitting diode comprising the substrate (1) and a production method for fabricating the nanowire structure is also provided. The production method utilizes non-epitaxial methods for forming the buffer layer (4).