公开(公告)号：US12027643B2

公开(公告)日：2024-07-02

申请号：US17232287

申请日：2021-04-16

Applicant: ALEDIA ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Eric Pourquier ,  Hubert Bono

IPC: H01L33/08 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02 ,  H01L27/15 ,  H01L29/06 ,  H01L29/12 ,  H01L29/66 ,  H01L33/00 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/24 ,  H01L33/42 ,  H01L33/48 ,  H10B69/00 ,  H01L33/02

CPC classification number: H01L33/06 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02603 ,  H01L27/15 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/127 ,  H01L29/6609 ,  H01L29/66469 ,  H01L33/0008 ,  H01L33/0062 ,  H01L33/007 ,  H01L33/0095 ,  H01L33/08 ,  H01L33/16 ,  H01L33/18 ,  H01L33/24 ,  H01L33/42 ,  H01L33/48 ,  H10B69/00 ,  H01L33/02 ,  H01L2924/0002 ,  H01L2933/0016 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for producing at least two adjacent regions, each comprising an array of light-emitting wires connected together in a given region by a transparent conductive layer, comprises: producing, on a substrate, a plurality of individual zones for growing wires extending over an area greater than the cumulative area of the two chips; growing wires in the individual growth zones; removing wires from at least one zone forming an initial free area to define the arrays of wires, the initial free area comprising individual growth zones level with the removed wires; and depositing a transparent conductive layer on each array of wires to electrically connect the wires of a given array of wires, each conductive layer being separated from the conductive layer of the neighbouring region by a free area. A device obtained using the process of the invention is also provided.

公开(公告)号：US20180233534A1

公开(公告)日：2018-08-16

申请号：US15891385

申请日：2018-02-08

Applicant: FUJI XEROX CO.,LTD.

Inventor： Takashi KONDO

IPC: B41J2/385 ,  H01L27/15 ,  H01S5/026 ,  H01S5/187 ,  H01L29/744 ,  H01L29/66 ,  H01L21/306 ,  H01L31/111 ,  H01S5/042 ,  H01L33/06 ,  H01L33/30 ,  H01L29/267 ,  H05B33/08 ,  H01L33/00 ,  H01L21/02 ,  H01L29/36 ,  H01L29/12 ,  H01L29/20 ,  H01L33/32 ,  H01S5/343 ,  H01L29/74

CPC classification number: H01L27/15 ,  G03G15/04054 ,  G03G15/04072 ,  G03G15/043 ,  G03G15/18 ,  G03G2215/0404 ,  G03G2215/0409 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/30612 ,  H01L25/0655 ,  H01L29/125 ,  H01L29/127 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/36 ,  H01L29/452 ,  H01L29/66401 ,  H01L29/7412 ,  H01L29/744 ,  H01L29/745 ,  H01L31/1113 ,  H01L33/0016 ,  H01L33/0041 ,  H01L33/0062 ,  H01L33/0066 ,  H01L33/06 ,  H01L33/30 ,  H01L33/32 ,  H01L33/40 ,  H01L33/44 ,  H01L33/62 ,  H01L2933/0025 ,  H01S5/026 ,  H01S5/0261 ,  H01S5/042 ,  H01S5/0421 ,  H01S5/0425 ,  H01S5/062 ,  H01S5/06203 ,  H01S5/18313 ,  H01S5/18361 ,  H01S5/18369 ,  H01S5/18377 ,  H01S5/187 ,  H01S5/2022 ,  H01S5/2027 ,  H01S5/2059 ,  H01S5/32 ,  H01S5/34313 ,  H01S5/34333 ,  H01S2304/02 ,  H01S2304/04 ,  H04N1/02865 ,  H04N1/40025 ,  H04N1/40056 ,  H05B33/0806

Abstract: A layered structure includes a thyristor and a light-emitting element. The thyristor at least includes four layers. The four layers are an anode layer, a first gate layer, a second gate layer, and a cathode layer arranged in this order. The light-emitting element is disposed such that the light-emitting element and the thyristor are connected in series. The thyristor includes a semiconductor layer having a bandgap energy smaller than bandgap energies of the four layers.

公开(公告)号：US09972797B2

公开(公告)日：2018-05-15

申请号：US15650874

申请日：2017-07-15

Applicant: International Business Machines Corporation

Inventor： Ali Afzali-Ardakani ,  Tze-Chiang Chen ,  Kailash Gopalakrishnan ,  Bahman Hekmatshoartabari

IPC: H01L29/06 ,  H01L31/00 ,  H01L51/05 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L29/778 ,  G06N3/063 ,  G11C11/54 ,  H01L29/12 ,  H01L29/10 ,  H01L29/43 ,  H01L29/51 ,  H01L51/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L51/0566 ,  G06N3/063 ,  G06N3/0635 ,  G11C11/54 ,  H01L21/28273 ,  H01L21/8238 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/1029 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/125 ,  H01L29/127 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42324 ,  H01L29/432 ,  H01L29/51 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/7881 ,  H01L51/0055 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/0562 ,  H01L2251/301

Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

公开(公告)号：US20170194357A1

公开(公告)日：2017-07-06

申请号：US15228141

申请日：2016-08-04

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/308 ,  H01L29/10 ,  H01L27/088 ,  H01L29/66 ,  H01L29/165 ,  H01L29/423

CPC classification number: H01L27/1211 ,  B82Y10/00 ,  H01L21/3081 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/125 ,  H01L29/165 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66818 ,  H01L29/775

Abstract: A threshold voltage tuning approach for forming a stacked nanowire gate-all around pFET is provided. In the present application, selective condensation (i.e., oxidation) is used to provide a threshold voltage shift in silicon germanium alloy nanowires. The threshold voltage shift is well controlled because both underlying parameters which govern the final germanium content, i.e., nanowire width and amount of condensation, are well controlled by the selective condensation process. The present application can address the problem of width quantization in stacked nanowire FETs by offering various device options.

公开(公告)号：US09287412B2

公开(公告)日：2016-03-15

申请号：US13465872

申请日：2012-05-07

Applicant: Faquir Chand Jain

Inventor： Faquir Chand Jain

IPC: H01L29/78 ,  H01L29/788 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/078 ,  H01L29/12 ,  G11C16/04 ,  B82Y20/00 ,  H01L29/06

CPC classification number: H01L29/7881 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y40/00 ,  G11C16/0408 ,  H01L21/28273 ,  H01L29/0665 ,  H01L29/125 ,  H01L29/42332 ,  H01L29/66825 ,  H01L31/028 ,  H01L31/035218 ,  H01L31/035236 ,  H01L31/078 ,  Y02E10/547

Abstract: This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories.

Abstract translation: 本发明描述了一种场效应晶体管，其中沟道形成为量子点阵列。 在一个实施例中，量子点用作为能量屏障的薄层包覆。 量子点通道（QDC）可以由一层或多层包层点组成。 这些点在单个或多晶衬底上实现。 当在多晶或纳米晶体薄膜上实现QDC FET时，它们可以产生比常规纳米或微晶薄膜更高的迁移率。 这些FET可用作各种应用中的薄膜晶体管（TFT）。 在另一个实施例中，QDC​​-FET与以下组合：（a）耦合量子阱SWS通道，（b）量子点栅3态状态，以及（c）量子点栅非易失性存储器。

公开(公告)号：US09147615B2

公开(公告)日：2015-09-29

申请号：US14181245

申请日：2014-02-14

Applicant: International Business Machines Corporation

Inventor： Ali Afzali-Ardakani ,  Tze-Chiang Chen ,  Kailash Gopalakrishnan ,  Bahman Hekmatshoartabari

IPC: H01L21/20 ,  H01L21/8238 ,  H01L29/778 ,  H01L29/66 ,  H01L29/267 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L51/0566 ,  G06N3/063 ,  G06N3/0635 ,  G11C11/54 ,  H01L21/28273 ,  H01L21/8238 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/1029 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/125 ,  H01L29/127 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42324 ,  H01L29/432 ,  H01L29/51 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/7881 ,  H01L51/0055 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/0562 ,  H01L2251/301

Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

Abstract translation: 基于捕获和去除捕获空穴或电子和/或两种载体的复合的装置结构通过在接近界面深双极态或量子阱/点中的载流子捕获来获得，其用作半导体层中的双极阱，或者 在栅介质/阻挡层中。 在任一情况下，捕获的势垒很小，并且通过在深陷阱状态和/或量子阱/点中的载流子限制提供保留。 设备架构可用作三个终端或两个终端设备。

公开(公告)号：US09087896B2

公开(公告)日：2015-07-21

申请号：US14048502

申请日：2013-10-08

Applicant: Jonas Ohlsson ,  Lars Samuelson ,  Erik Lind ,  Lars-Erik Wernersson ,  Truls Lowgren

Inventor： Jonas Ohlsson ,  Lars Samuelson ,  Erik Lind ,  Lars-Erik Wernersson ,  Truls Lowgren

IPC: H01L29/66 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/12 ,  H01L29/775 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L33/24

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7828 ,  H01L29/78642 ,  H01L33/24 ,  Y10S977/888 ,  Y10S977/89

Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

Abstract translation: 本发明涉及在垂直半导体器件（1）的垂直和水平表面（15,20）上提供不同厚度的层。 特别地，本发明涉及栅电极和在半导体结构中形成精密层（28），该半导体结构包括基底（10）和基本上从基底上竖立的细长结构（5）。 根据本发明的方法，将装置（1）的垂直几何结构与各向异性沉积或各向异性去除沉积材料结合使用以形成非常高精度的垂直或水平层。

公开(公告)号：US08790998B2

公开(公告)日：2014-07-29

申请号：US12588828

申请日：2009-10-29

Applicant: Ki-ha Hong ,  Kyoung-won Park ,  Jai-kwang Shin ,  Jong-seob Kim ,  Hyuk-soon Choi

Inventor： Ki-ha Hong ,  Kyoung-won Park ,  Jai-kwang Shin ,  Jong-seob Kim ,  Hyuk-soon Choi

IPC: H01L21/302 ,  H01L21/336 ,  H01L21/84 ,  H01L21/20 ,  H01L29/12 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/125 ,  B82Y10/00 ,  H01L29/127 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696 ,  Y10T156/10 ,  Y10T156/1082

Abstract: Example embodiments relate to a method of forming a core-shell structure. According to a method, a region in which the core-shell structure will be formed is defined on a substrate, and a core and a shell layer may be sequentially stacked in the defined region. A first shell layer may further be formed between the substrate and the core. When the core and the shell layer are sequentially stacked in the core-shell region, the method may further include forming a groove on the substrate, forming the first shell layer covering surfaces of the groove, forming the core in the groove of which surfaces are covered by the first shell layer, and forming a second shell layer covering the core.

Abstract translation: 示例性实施例涉及形成核 - 壳结构的方法。 根据一种方法，在基板上限定形成芯 - 壳结构的区域，并且可以在限定区域中顺序堆叠芯层和壳层。 第一壳层可以进一步形成在衬底和芯之间。 当核心层和壳层依次层叠在芯 - 壳区域中时，该方法还可以包括在基板上形成凹槽，形成覆盖凹槽表面的第一壳层，在其表面的凹槽中形成芯 被第一壳层覆盖，并且形成覆盖芯的第二壳层。

公开(公告)号：US08765539B2

公开(公告)日：2014-07-01

申请号：US14155972

申请日：2014-01-15

Applicant: International Business Machines Corporation

Inventor： Joerg Appenzeller ,  Supratik Guha ,  Emanuel Tutuc

IPC: H01L21/336

CPC classification number: H01L21/30604 ,  B82Y10/00 ,  H01L21/02603 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1041 ,  H01L29/125 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.

Abstract translation: 提供了一种半导体结构，其包括沿纵向轴线布置的多个部分。 优选地，半导体结构包括位于中间部分的相对端的中间部分和两个端子部分。 具有第一掺杂剂浓度的半导体芯片优选地沿着纵向轴线延伸通过中间部分和两个端子部分。 具有第二较高掺杂剂浓度的半导体壳体优选地环绕半导体结构的两个端子部分但不在中间部分处的半导体芯体的一部分。 特别优选的是，半导体结构是具有不大于100nm的横截面尺寸的纳米结构。

公开(公告)号：US20140166985A1

公开(公告)日：2014-06-19

申请号：US14240219

申请日：2012-08-21

Applicant: Makoto Kohda ,  Junsaku Nitta ,  Kensuke Kobayashi

Inventor： Makoto Kohda ,  Junsaku Nitta ,  Kensuke Kobayashi

IPC: H01L43/06

CPC classification number: H01L43/065 ,  B82Y10/00 ,  H01F10/00 ,  H01L27/222 ,  H01L29/0673 ,  H01L29/125 ,  H01L29/205 ,  H01L29/42356 ,  H01L29/66984 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/82 ,  H01L29/861 ,  H01L43/08 ,  H01L43/10

Abstract: A rectifying device includes: a one-dimensional channel (18) formed with a semiconductor, electrons traveling through the one-dimensional channel; an electrode (26) that applies an effective magnetic field generated from a spin orbit interaction to the electrons traveling through the one-dimensional channel by applying an electric field to the one-dimensional channel, the effective magnetic field being in a direction intersectional to the direction in which the electrons are traveling; and an external magnetic field generating unit (38) that generates an external magnetic field in the one-dimensional channel.

Abstract translation: 整流装置包括：形成有半导体的一维沟道（18），穿过该一维沟道的电子; 电极（26），其通过向所述一维通道施加电场，将从自旋轨道相互作用产生的有效磁场施加到穿过所述一维通道的电子，所述有效磁场位于与所述一维通道相交的方向上 电子行进的方向; 以及在一维通道中产生外部磁场的外部磁场产生单元（38）。