公开(公告)号：US07340545B2

公开(公告)日：2008-03-04

申请号：US11203733

申请日：2005-08-15

申请人： Dwight D. Riley

发明人： Dwight D. Riley

IPC分类号： G06F13/362

CPC分类号： G06F13/423

摘要： There is provided a distributed peer-to-peer communication system for interconnect busses of a computer system. More specifically, there is provided a method comprising transmitting a request to establish an isochronous channel between a first device and a second device, establishing the isochronous channel between the first device and the second device, and generating an isochronous transaction across the isochronous channel between the first device and the second device, wherein the isochronous transaction is a message type transaction.

摘要翻译： 提供了一种用于计算机系统的互连总线的分布式对等通信系统。 更具体地，提供了一种方法，包括发送在第一设备和第二设备之间建立同步信道的请求，在第一设备和第二设备之间建立同步信道，以及在等时信道之间生成同步事务 第一设备和第二设备，其中等时事务是消息类型事务。

公开(公告)号：US06801970B2

公开(公告)日：2004-10-05

申请号：US09968056

申请日：2001-09-30

申请人： Dwight D. Riley ,  Chris Pettey

发明人： Dwight D. Riley ,  Chris Pettey

IPC分类号： G06F1340

CPC分类号： G06F13/423 ,  G06F2213/0024

摘要： Support for indicating and controlling transaction priority on a PCI-X bus. Embodiments of the invention provide indicia that can be set to communicate to PCI-X-to-PCI-X bridges and Completer that a transaction should be handled specially and scheduled ahead of any other transaction not having their corresponding indicia set. A special handling instruction allows the priority transaction to be scheduled first or early. The indicia are implemented by setting a bit(s) in an unused portion of a PCI-X attribute field, or multiplexed with a used portion, to schedule the associated transaction as the priority transaction over other transactions that do not have their corresponding bit set. The present invention can be used for interrupt messaging, audio streams, video streams, isochronous transactions, or for high performance, low bandwidth control structures used for communication in a multiprocessor architecture across PCI-X.

摘要翻译： 支持指示和控制PCI-X总线上的事务优先级。 本发明的实施例提供了可以设置为与PCI-X到PCI-X网桥通信的标记，并且完成事务应当在没有其对应标记集的任何其他事务之前特别处理和调度。 特殊处理指令允许首先或早期安排优先级事务。 通过在PCI-X属性字段的未使用部分中设置一个或多个与所使用的部分进行复用的位来实施该标记，以将相关联的事务调度为不具有其对应位集合的其他事务的优先级事务 。 本发明可以用于中断消息传递，音频流，视频流，等时事务处理，或用于跨PCI-X的多处理器架构中用于通信的高性能，低带宽控制结构。

公开(公告)号：US06247087B1

公开(公告)日：2001-06-12

申请号：US09036634

申请日：1998-03-06

申请人： Dwight D. Riley ,  David J. Maguire

发明人： Dwight D. Riley ,  David J. Maguire

IPC分类号： G06F1300

CPC分类号： G06F13/4027

摘要： The present invention relates to a system and method for shadowing data of a first register and a second register of a computer system that share a common address. When a bus agent runs a write operation to the register address, retry logic of a first bridge circuit retries the write operation and masks access by the bus agent to the bus. Retry bus master logic reruns the write operation, in response to which the second bridge circuit subtractively decodes the rerun write operation and transfers the data to the second register. The bus agent is then allowed to retry the initial write operation, in response to which the first bridge circuit positively decodes the retried write operation and transfers the data to the first register. Thus, coherency is preserved between the first and second registers.

摘要翻译： 本发明涉及一种用于对共享共同地址的计算机系统的第一寄存器和第二寄存器的数据进行阴影化的系统和方法。 当总线代理对寄存器地址执行写入操作时，第一桥接电路的重试逻辑重试写入操作，并掩盖总线代理对总线的访问。 重试总线主机逻辑重新执行写入操作，响应于此，第二桥接电路对该重新运行写入操作进行减法解码并将数据传送到第二寄存器。 然后允许总线代理重试初始写操作，响应于此，第一桥电路对其进行重试写入操作，并将数据传送到第一寄存器。 因此，在第一和第二寄存器之间保持一致性。

公开(公告)号：US20090037609A1

公开(公告)日：2009-02-05

申请号：US11830747

申请日：2007-07-30

申请人： Dwight D. Riley ,  James X. Dinh ,  Barry S. Basile ,  Kenneth A. Jansen ,  Hubert E. Brinkmann ,  David L. Matthews ,  Paul V. Brownell

发明人： Dwight D. Riley ,  James X. Dinh ,  Barry S. Basile ,  Kenneth A. Jansen ,  Hubert E. Brinkmann ,  David L. Matthews ,  Paul V. Brownell

IPC分类号： G06F3/00

CPC分类号： G06F3/0227

摘要： A middle manager and methods are provided to enable a plurality of host devices to share one or more input/output devices. The middle manager initializes each shared input/output device and binds one or more functions of each input/output device to a specific host node in the system, such that hosts may only access functions to which they are bound. The middle manager may also utilize a configuration register map to translate values from the actual configuration register into a unique modified value for each of the plurality of host devices such that each host device may access and use the shared input/output device regardless of the firmware or operating system operating thereon.

公开(公告)号：US20090010159A1

公开(公告)日：2009-01-08

申请号：US11825492

申请日：2007-07-06

申请人： Paul V. Brownell ,  David L. Matthews ,  James Xuan Dinh ,  Hubert E. Brinkmann ,  Dwight D. Riley ,  Hahn Vo Norden ,  Kenneth T. Chin

发明人： Paul V. Brownell ,  David L. Matthews ,  James Xuan Dinh ,  Hubert E. Brinkmann ,  Dwight D. Riley ,  Hahn Vo Norden ,  Kenneth T. Chin

IPC分类号： H04L12/26

CPC分类号： H04L47/263 ,  H04L41/08 ,  H04L47/18 ,  H04L47/215 ,  H04L47/30 ,  H04L47/39 ,  H04L2212/00

摘要： A network node within a network includes a first receive buffer, first buffer management, a second receive buffer and second buffer management. The first buffer management performs link level credit based flow control for network packets that the first buffer management places in the first receive buffer. The second buffer management performs end-to-end credit based flow control for network packets that the second buffer management receives from the first receive buffer and processes before placing data in the second receive buffer.

摘要翻译： 网络内的网络节点包括第一接收缓冲器，第一缓冲器管理，第二接收缓冲器和第二缓冲器管理。 第一缓冲器管理对第一缓冲器管理放置在第一接收缓冲器中的网络分组执行基于链路级信用的流量控制。 第二缓冲器管理对第二缓冲器管理从第一接收缓冲器接收的网络分组执行基于端到端的信用流量控制，并且在将数据置于第二接收缓冲器之前进行处理。

公开(公告)号：US07447975B2

公开(公告)日：2008-11-04

申请号：US10243995

申请日：2002-09-12

申请人： Dwight D. Riley

发明人： Dwight D. Riley

IPC分类号： H03M13/00

CPC分类号： G06F11/10 ,  H03M13/09

摘要： A cyclic redundancy check (CRC) mechanism for the extensions (PCI-X) to the Peripheral Component Interconnect (PCI) bus system used in computer systems is fully backward compatible with the full PCI-X protocol. CRC check-bits are inserted to provide error detection capability for the header address and attribute phases, and for burst and DWORD transaction data phases. The CRC check-bits are inserted into unused attribute or clock (or target response) phases, or into reserved or reserved drive high portions (bits) of the address/data (AD), command/byte enable (C/BE#), or into the parity lanes of the PCI-X phases.

摘要翻译： 用于计算机系统中使用的外围组件互连（PCI）总线系统的扩展（PCI-X）的循环冗余校验（CRC）机制与完整的PCI-X协议完全向后兼容。 插入CRC校验位以提供头部地址和属性阶段以及突发和DWORD事务数据阶段的错误检测能力。 CRC校验位被插入到未使用的属性或时钟（或目标响应）阶段中，或者被插入到地址/数据（AD），命令/字节使能（C / BE＃）的预留或保留的驱动器高部分（位） 或进入PCI-X阶段的奇偶通道。

公开(公告)号：US07096306B2

公开(公告)日：2006-08-22

申请号：US10209846

申请日：2002-07-31

申请人： Dwight D. Riley

发明人： Dwight D. Riley

IPC分类号： G06F13/20 ,  G06F13/36

CPC分类号： G06F15/17375

摘要： An aliasing technique allows transparently connecting multiple interconnects across a shared cross-connect interconnect, allowing devices on one interconnect to communicate with devices on another interconnect as if both interconnects were connected by a single interconnect bridge. Each interconnect appears to the cross-connect interconnect as a device on the cross-connect interconnect. Transactions between devices on different interconnects are aliased by a routing engine connected to the cross-connect interconnect for transmittal across the cross-connect interconnect and are invisible to other transactions on the cross-connect interconnect. Transactions between devices on the same interconnect are invisible to other interconnects. Cache coherent requests are supported by the use of additional attribute bits.

摘要翻译： 混叠技术允许跨共享的交叉连接互连透明地连接多个互连，允许一个互连上的设备与另一个互连上的设备进行通信，就好像两个互连通过单个互连桥连接。 每个互连在交叉连接互连上显示为交叉连接互连上的设备。 不同互连设备之间的事务由连接到交叉连接互连的路由引擎进行混叠，以跨越交叉连接互连传输，并且对于交叉连接互连上的其他事务是不可见的。 在相同互连上的设备之间的事务对于其他互连是不可见的。 通过使用附加属性位来支持缓存一致请求。

公开(公告)号：US06449677B1

公开(公告)日：2002-09-10

申请号：US09266356

申请日：1999-03-11

申请人： Sompong Paul Olarig ,  Thomas R. Seeman ,  Kenneth Jansen ,  Dwight D. Riley

发明人： Sompong Paul Olarig ,  Thomas R. Seeman ,  Kenneth Jansen ,  Dwight D. Riley

IPC分类号： G06F1338

CPC分类号： G06F13/105

摘要： A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. Alternate embodiments of the present invention utilize a side-band address port (SBA port) to enable multiple targets to receive the same set of data. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction. Some extended command encodings are reserved but can be assigned in the future to new extended commands that will behave in a predictable manner with current devices.

摘要翻译： 为数字计算机系统上的外围组件提供高速连接装置，方法和系统。 外围组件互连（PCI）规范用作扩展命令和属性集的基准。 扩展命令和属性在发出初始命令的时钟周期之后的时钟周期内在总线上发出。 扩展的命令和属性利用常规PCI设备和总线的标准引脚连接，使本发明与现有（常规）PCI设备和传统计算机系统向后兼容。 本发明的替代实施例利用边带地址端口（SBA端口）使多个目标能够接收相同的数据集。 传统的PCI命令编码被修改，扩展命令用于限定事务类型和事务发起者使用的属性。 一些扩展的命令编码被保留，但可以将来分配给新的扩展命令，该扩展命令将以可预测的方式与当前设备一起运行。

公开(公告)号：US5774680A

公开(公告)日：1998-06-30

申请号：US570394

申请日：1995-12-11

申请人： Christopher C. Wanner ,  Jeffrey C. Stevens ,  Robert A. Lester ,  Dwight D. Riley ,  David J. Maguire ,  James Edwards

发明人： Christopher C. Wanner ,  Jeffrey C. Stevens ,  Robert A. Lester ,  Dwight D. Riley ,  David J. Maguire ,  James Edwards

IPC分类号： G06F13/12 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28 ,  G06F13/126

摘要： A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

公开(公告)号：US08316377B2

公开(公告)日：2012-11-20

申请号：US11851306

申请日：2007-09-06

申请人： Dwight D. Riley

发明人： Dwight D. Riley

IPC分类号： G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00

CPC分类号： H04L49/35 ,  H04L49/65

摘要： Systems and methods of sharing legacy devices in a multi-host environment are disclosed. An exemplary method for sharing legacy devices in a multi-host environment includes receiving device information from a legacy device, the device information identifying a target within a virtual machine. The method also includes encapsulating the device information into a corresponding bus transaction for a network switch fabric. The method also includes routing the bus transaction over the network switch fabric in the virtual machine to a host within the virtual machine.

摘要翻译： 公开了在多主机环境中共享传统设备的系统和方法。 用于在多主机环境中共享传统设备的示例性方法包括从传统设备接收设备信息，所述设备信息标识虚拟机内的目标。 该方法还包括将设备信息封装成用于网络交换结构的相应总线事务。 该方法还包括将虚拟机中的网络交换机结构上的总线事务路由到虚拟机内的主机。