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1.发明授权Method and apparatus for multiplexing and demultiplexing addresses of registered peripheral interconnect apparatus 有权用于复用和解复用注册的外围互连设备的地址的方法和装置公开(公告)号：US06449677B1
公开(公告)日：2002-09-10
申请号：US09266356
申请日：1999-03-11
IPC分类号： G06F1338
CPC分类号： G06F13/105
摘要： A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. Alternate embodiments of the present invention utilize a side-band address port (SBA port) to enable multiple targets to receive the same set of data. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction. Some extended command encodings are reserved but can be assigned in the future to new extended commands that will behave in a predictable manner with current devices.
摘要翻译： 为数字计算机系统上的外围组件提供高速连接装置，方法和系统。 外围组件互连（PCI）规范用作扩展命令和属性集的基准。 扩展命令和属性在发出初始命令的时钟周期之后的时钟周期内在总线上发出。 扩展的命令和属性利用常规PCI设备和总线的标准引脚连接，使本发明与现有（常规）PCI设备和传统计算机系统向后兼容。 本发明的替代实施例利用边带地址端口（SBA端口）使多个目标能够接收相同的数据集。 传统的PCI命令编码被修改，扩展命令用于限定事务类型和事务发起者使用的属性。 一些扩展的命令编码被保留，但可以将来分配给新的扩展命令，该扩展命令将以可预测的方式与当前设备一起运行。
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2.发明申请HETEROGENEOUS COMPUTING SYSTEM COMPRISING A SWITCH/NETWORK ADAPTER PORT INTERFACE UTILIZING LOAD-REDUCED DUAL IN-LINE MEMORY MODULES (LR-DIMMS) INCORPORATING ISOLATION MEMORY BUFFERS 审中-公开包含开关/网络适配器端口接口的异构计算系统利用负载减少的双向在线存储器模块（LR-DIMMS）并入隔离存储器缓冲器公开(公告)号：US20120117318A1
公开(公告)日：2012-05-10
申请号：US13286996
申请日：2011-11-01
IPC分类号： G06F12/00
CPC分类号： G06F13/1663
摘要： A heterogeneous computing system comprising a switch/network adapter port interface utilizing load-reduced dual in-line memory modules (LR-DIMMs) incorporating isolation memory buffers. In a particular embodiment of the present invention the computer system comprises at least one dense logic device and a controller coupling it to a memory bus. A plurality of memory slots are coupled to the memory bus and an adaptor port is associated with some number of the plurality of memory slots, each of the adapter ports including associated memory resources. A direct execution logic element is coupled to at least one of the adapter ports. The memory resources are selectively accessible by the at least one dense logic device and the direct execution logic element.
摘要翻译： 异构计算系统包括利用负载减少的双列直插存储器模块（LR-DIMM）并入隔离存储器缓冲器的交换机/网络适配器端口接口。 在本发明的特定实施例中，计算机系统包括至少一个密集逻辑设备和将其耦合到存储器总线的控制器。 多个存储器插槽耦合到存储器总线，并且适配器端口与若干数量的多个存储器插槽相关联，每个适配器端口包括相关联的存储器资源。 直接执行逻辑元件耦合到至少一个适配器端口。 存储器资源可由至少一个密集逻辑器件和直接执行逻辑元件选择性地访问。
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3.发明授权
公开(公告)号：US6148359A
公开(公告)日：2000-11-14
申请号：US186597
申请日：1998-11-05
CPC分类号： G06F13/4027 , G06F13/4059
摘要： A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-EISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches the bridge interface from the bridge or PCI bus, and it is recognized that the address is within the range, then the fast burst mode is allowed, and write addresses are allowed to follow one another without the delay for the snoop phase or the possibility of defer or retry.
摘要翻译： 计算机系统在微处理器本身的控制下具有处理器总线，并且该总线与主存储器通信，为大多数缓存填充操作提供高性能访问。 此外，该系统包括一个或多个扩展总线，优选地在示例性实施例中为PCI类型。 主机到PCI桥接器用于将处理器总线耦合到扩展总线。 例如，其他总线可以通过PCI-to-EISA桥耦合到PCI总线。 主机到PCI桥接器包含发布的写入和延迟读取请求的队列。 所有交易排队通过桥梁，上游或下游。 系统总线是超级管道，因为交易重叠。 在桥接器和主存储器之间允许快速突发事务，即，可以在不延迟或重试的情况下满足的请求被应用于系统总线，而不等待从目标获得响应。 地址范围（例如，系统存储器地址）被定义为快速突发范围，并且该范围内的任何地址与该范围之外的地址不同。 通过配置周期对桥进行编程，以建立此快速突发范围，在此范围内，已知无法接收到无序响应。 当事务从桥接器或PCI总线到达桥接口时，并且认识到地址在该范围内，则允许快速突发模式，并且允许写入地址彼此跟随，而没有窥探阶段的延迟 或延迟或重试的可能性。
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4.发明授权Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers 有权交换机/网络适配器端口将可重配置处理元件耦合到一个或多个微处理器以与交错存储器控制器一起使用公开(公告)号：US07197575B2
公开(公告)日：2007-03-27
申请号：US10340390
申请日：2003-01-10
IPC分类号： G06F15/16
CPC分类号： G06F13/1663 , G06F13/1684
摘要： A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.
摘要翻译： 双串行内存模块（“DIMM”）或Rambus（TM）在线内存模块（“RIMM”）格式的交换机/网络适配器端口（“SNAP（TM）”），用于采用多自适应 处理器（“MAP（R）”，SRC Computers，Inc.的两个商标）用于交错存储器控制器的元件。 特别公开的是基于微处理器的计算机系统，其利用耦合到可重构处理器元件的DIMM或RIMM物理格式适配器端口来实现到外部交换机，网络或其他设备的连接。 在特定实施例中，连接可以被提供给PCI，加速图形端口（“AGP”）或系统维护（“SM”）总线，用于将控制信息传递到主微处理器或其他控制芯片。 基于现场可编程门阵列（“FPGA”）的处理元件具有将数据传送到外部互连结构或设备的能力。
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公开(公告)号：US5832243A
公开(公告)日：1998-11-03
申请号：US775301
申请日：1996-12-31
申请人： Thomas R. Seeman
发明人： Thomas R. Seeman
CPC分类号： G06F13/4027 , Y02B60/1228 , Y02B60/1235
摘要： A computer system using posted memory write buffers in a bridge can implement the stop clock acknowledge special cycle without faulty operation. The stop clock acknowledge transaction is posted in bridge buffers so that any previously posted memory write commands currently held in a posted memory write buffer in the bridge execute prior to the appearance of the posted stop clock acknowledge transaction. In this way, bridges having both posted write buffers and the stop clock special cycle may be utilized in efficient joint operation.
摘要翻译： 在桥接器中使用发布的存储器写入缓冲器的计算机系统可以实现停止时钟确认特殊周期而没有错误的操作。 停止时钟确认事务被发布在桥接缓冲器中，使得当前保存在桥中的已发布的存储器写入缓冲器中的任何先前发布的存储器写入命令在出现停止时钟确认事务之前执行。 以这种方式，可以在有效的联合操作中使用具有发送的写缓冲器和停止时钟特殊周期的桥。
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公开(公告)号：US07421524B2
公开(公告)日：2008-09-02
申请号：US10996016
申请日：2004-11-23
IPC分类号： G06F13/12
CPC分类号： G06F15/7867 , G06F13/4027
摘要： A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.
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">7.发明授权Lock protocol for PCI bus using an additional "superlock" signal on the system bus 失效使用系统总线上附加“超级锁”信号的PCI总线锁定协议
公开(公告)号：US6098134A
公开(公告)日：2000-08-01
申请号：US775130
申请日：1996-12-31
CPC分类号： G06F9/52
摘要： A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E)ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available. A contemporary microprocessor such as a P6 has a deferred transaction protocol to implement split transactions, but this protocol is not available on a PCI bus. Split transactions are done by a "retry" command on a PCI bus, wherein a read request that cannot be completed immediately is queued and a "retry" response is sent back to the requester on the bus; this instructs the requester to retry (send the same command again) at a later time. To avoid a situation where two processors issue locked cycles which are enqueued and retried in separate bridges, a "Superlock" signal is added to the processor bus, which is asserted by a bridge as soon as a locked transaction is enqueued, and thereafter neither bridge will accept a locked cycle issued by a processor, other than that locked read that was initiated by a processor and enqueued in the bridge and is being retried.
摘要翻译： 计算机系统在微处理器本身的控制下具有处理器总线，并且该总线与主存储器通信，为大多数缓存填充操作提供高性能访问。 此外，该系统包括一个或多个扩展总线，优选地在示例性实施例中为PCI类型。 主机到PCI桥接器用于将处理器总线耦合到扩展总线。 例如，其他总线可以通过PCI至（E）ISA网桥耦合到PCI总线。 主机到PCI桥接器包含发布的写入和延迟读取请求的队列。 所有交易排队通过桥梁，上游或下游。 根据本发明的特征，提供分割事务，即，在请求它的处理器仍然在总线上时不满足的读请求，而是在读取结果为止之前放弃总线并且其他事务干预 可用。 诸如P6的当代微处理器具有延迟事务协议来实现分离事务，但是该协议在PCI总线上不可用。 拆分事务通过PCI总线上的“重试”命令完成，其中立即不能完成的读取请求被排队，并且“重试”响应被发送回总线上的请求者; 这指示请求者稍后重试（再次发送相同的命令）。 为了避免两个处理器发出锁定循环的情况，这些循环在单独的桥接器中排队并重试，“Superlock”信号被添加到处理器总线中，一旦锁定的事务被入队就由桥接器断言，然后两个桥接器 将接受处理器发出的锁定循环，而不是由处理器启动并处于桥中并正在重试的锁定读取。
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8.发明申请公开(公告)号：US20130157639A1
公开(公告)日：2013-06-20
申请号：US13365090
申请日：2012-02-02
IPC分类号： H04W4/00
CPC分类号： G06F1/3234 , G06F17/5054 , G06F2217/78 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： Disclosed herein are mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption for, inter alia, increased device battery life. The techniques disclosed herein enable greatly enhanced compression/decompression as well as encryption and decryption functionality to be provided in addition to overall greater processing capability particularly in those applications wherein minimization of power consumption is desired. Package-on-package and other assembly techniques may be used to provide the reconfigurable processor in a small footprint package.
摘要翻译： 本文公开了使用可重构处理技术的移动电子设备，以便特别是增加设备电池寿命来实现具有降低的功率消耗的更高速度应用。 除了总体更大的处理能力之外，本文公开的技术能够大大增强压缩/解压缩以及加密和解密功能，特别是在需要最小化功耗的那些应用中。 封装封装和其他装配技术可用于以小尺寸封装提供可重构处理器。
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9.再颁专利公开(公告)号：USRE37980E1
公开(公告)日：2003-02-04
申请号：US09706883
申请日：2000-11-03
IPC分类号： G06F1300
CPC分类号： G06F13/4027 , G06F13/4059
摘要： A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches a bridge interface from the PCI bus, and it is recognized that the address is within the fast burst range, then the fast burst mode is allowed, and write or read requests can be issued without waiting for the snoop phase, since there is no possibility of defer or retry.
摘要翻译： 计算机系统在微处理器本身的控制下具有处理器总线，并且该总线与主存储器通信，为大多数缓存填充操作提供高性能访问。 此外，该系统包括一个或多个扩展总线，优选地在示例性实施例中为PCI类型。 主机到PCI桥接器用于将处理器总线耦合到扩展总线。 例如，其他总线可以通过PCI至（E）ISA网桥耦合到PCI总线。 主机到PCI桥接器包含发布的写入和延迟读取请求的队列。 所有交易排队通过桥梁，上游或下游。 系统总线是超级管道，因为交易重叠。 在桥接器和主存储器之间允许快速突发事务，即，可以在不延迟或重试的情况下满足的请求被应用于系统总线，而不等待从目标获得响应。 地址范围（例如，系统存储器地址）被定义为快速突发范围，并且该范围内的任何地址与该范围之外的地址不同。 通过配置周期对桥进行编程，以建立此快速突发范围，在此范围内，已知无法接收到无序响应。 当事务从PCI总线到达桥接口时，并且认识到地址在快速突发范围内，则允许快速突发模式，并且可以发出写入或读取请求而不等待窥探阶段，因为 没有推迟或重试的可能性。
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10.发明授权Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers 有权交换机/网络适配器端口将可重配置处理元件耦合到一个或多个微处理器以与交错存储器控制器一起使用公开(公告)号：US07565461B2
公开(公告)日：2009-07-21
申请号：US11203983
申请日：2005-08-15
IPC分类号： G06F3/00
CPC分类号： G06F13/385 , G06F13/1652
摘要： A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.
摘要翻译： 双串行内存模块（“DIMM”）或Rambus（TM）在线内存模块（“RIMM”）格式的交换机/网络适配器端口（“SNAP（TM）”），用于采用多自适应 处理器（“MAP（R）”，SRC Computers，Inc.的两个商标）用于交错存储器控制器的元件。 特别公开的是基于微处理器的计算机系统，其利用耦合到可重构处理器元件的DIMM或RIMM物理格式适配器端口来实现到外部交换机，网络或其他设备的连接。 在特定实施例中，连接可以被提供给PCI，加速图形端口（“AGP”）或系统维护（“SM”）总线，用于将控制信息传递到主微处理器或其他控制芯片。 基于现场可编程门阵列（“FPGA”）的处理元件具有将数据传送到外部互连结构或设备的能力。
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