公开(公告)号：US20040212526A1

公开(公告)日：2004-10-28

申请号：US10810310

申请日：2004-03-26

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H03M001/66 ,  H03M001/00

CPC classification number: H03M1/0604 ,  H03M1/682 ,  H03M1/765

Abstract: An improved segmented analog to digital converter is provided, configured with a novel method of compensating current flow in secondary or successive segmented elements. In operation, dual current devices initially load, then subsequently unload a cascade of resistor networks connected to the secondary or successive voltage segmenting elements, preventing the perturbation of precise operation of the primary or preceding elements. In contrast to conventional approaches, the improved converter obviates the need for a buffer or amplifier to isolate the secondary and successive voltage segmenting elements from the primary or preceding elements.

Abstract translation: 提供了一种改进的分段模数转换器，其配置有补偿次级或连续分段元件中的电流的新颖方法。 在操作中，双电流装置最初加载，随后卸载连接到次级或连续电压分段元件的级联的电阻网络，以防止主要或先前元件的精确操作的扰动。 与常规方法相比，改进的转换器不需要缓冲器或放大器来隔离次级和连续的电压分段元件与初级元件或先前元件。

公开(公告)号：US20040193665A1

公开(公告)日：2004-09-30

申请号：US10453901

申请日：2003-06-02

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: G06F017/10

CPC classification number: H03M7/3004 ,  H03H17/0248 ,  H03M7/3028 ,  H03M7/3042

Abstract: The invention is directed to a bi-quad filter circuit configured with sigma-delta devices that operate as binary rate multipliers (BRMs). Unlike conventional bi-quad filter circuits, the invention provides a bi-quad filter configured with a single-bit BRM. In another embodiment, the invention further provides a bi-quad filter configured with multiple-bit BRMs.

Abstract translation: 本发明涉及一种双向滤波器电路，其配置为以二进制比率乘法器（BRM）操作的Σ-Δ器件。 与传统的双通道滤波器电路不同，本发明提供一种配置有单位BRM的双通道滤波器。 在另一个实施例中，本发明还提供一种配置有多位BRM的双二进制滤波器。

公开(公告)号：US20040145509A1

公开(公告)日：2004-07-29

申请号：US10687300

申请日：2003-10-15

Applicant: ESS Technology, Inc.

Inventor： Andrew Martin Mallinson

IPC: H03M001/36

CPC classification number: H03M1/0854 ,  H03M1/1235 ,  H03M1/144 ,  H03M1/206 ,  H03M1/367

Abstract: An analog-to-digital converter in which each of a plurality of comparators is, in a successive approximation manner, selectively enabled or disabled and the outputs from those comparators summed together to produce a digital signal therefrom. By weighting and mixing outputs of adjacent comparators in proportions calculated to provide an interpolated output of a virtual comparator between the actual comparators, many such virtual comparators can be created without the need for additional fixed hardware elements in the converter. By doing so, the converter is able to produce a digital output having n bits using only N actual hardware elements for comparing signals, where N