公开(公告)号：US20090299759A1

公开(公告)日：2009-12-03

申请号：US12132203

申请日：2008-06-03

申请人： Wayne M. Delia ,  Edward E. Kelley ,  Franco Motika

发明人： Wayne M. Delia ,  Edward E. Kelley ,  Franco Motika

IPC分类号： G06Q20/00

CPC分类号： H04L63/0428 ,  H04L63/083 ,  H04L63/1466

摘要： A method for constructing a secure Internet transaction, the method includes: receiving a user identification (userid) and user password on a client device for filling out a form generated by a secure web site; concatenating the user's Internet Protocol (IP) address with a separate password that is maintained on the secure web site that the user is authenticating to; encrypting the concatenated user IP and separate password to form an Internet Protocol password (IPPW); wherein the encrypting is carried out with a client device linear feedback shift register (LFSR) with a defined cycle count; building a transaction consisting of the IPPW, defined cycle count, and userid; transmitting the transaction and form via a network towards the secure web site; wherein in response the secure website performs the following: decrypts the IPPW, and determines if the IP portion of the decrypted IPPW is equal to the user's IP address.

摘要翻译： 一种用于构建安全因特网事务的方法，所述方法包括：在客户端设备上接收用户标识（用户ID）和用户密码，以填写由安全网站生成的表单; 将用户的因特网协议（IP）地址与在用户正在认证的安全网站上维护的单独的密码连接起来; 加密连接的用户IP和单独的密码以形成Internet协议密码（IPPW）; 其中所述加密是利用具有定义的周期计数的客户端设备线性反馈移位寄存器（LFSR）来执行的; 构建由IPPW，定义的循环计数和userid组成的事务; 通过网络向安全网站传送交易和表单; 其中作为响应，安全网站执行以下操作：解密IPPW，并确定解密的IPPW的IP部分是否等于用户的IP地址。

公开(公告)号：US20090217116A1

公开(公告)日：2009-08-27

申请号：US12036320

申请日：2008-02-25

申请人： Franco Motika ,  Michael R. Ouellette ,  Phong T. Tran

发明人： Franco Motika ,  Michael R. Ouellette ,  Phong T. Tran

IPC分类号： G06F11/00

CPC分类号： G01R31/318541 ,  G01R31/318536

摘要： A structural design-for-test for diagnosing broken scan chain defects of long non-scannable register chains (GPTR) The GPTR and the system for testing and diagnosing the broken LSSD scan-only chains rapidly localize defects to the failing Shift Register Latch (SRL) pair. The GPTR modifies the latches used in the GPTR scan chain to standard LSSD L1/L2 master-slave SRL type latch pairs; connects all the system ports of the L1 latches to the Shift Register Input (SRI) and clocked by the system C1-clk while the L1 scan port is clocked by the A-clk and L2 scan port is clocked only by the B-clk. The L1 latches are connected to at least one multiplexer having a first output connected to an input of each odd SRL, and a second output connected to an input port of each even SRL. In another embodiment, the GPTR includes a plurality of multiplexers respectively coupled to the master-slave latch pairs, wherein a first set of multiplexers have their respective output attached to an input of the odd L1 latches, and a second set of the multiplexers have their respective output attached to an input port of the even L1 latches.

摘要翻译： 用于诊断长不可扫描寄存器链（GPTR）的断层扫描链缺陷的结构设计 - 用于测试和诊断断裂的LSSD扫描链的系统快速将缺陷定位到故障移位寄存器锁存器（SRL） ）对。 GPTR将GPTR扫描链中使用的锁存器修改为标准LSSD L1 / L2主从SL型锁存器对; 将L1锁存器的所有系统端口连接到移位寄存器输入（SRI）并由系统C1-clk计时，而L1扫描端口由A-clk计时，L2扫描端口由B-clk提供时钟。 L1锁存器连接到至少一个多路复用器，其具有连接到每个奇数SRL的输入的第一输出，以及连接到每个偶数SRL的输入端口的第二输出。 在另一个实施例中，GPTR包括分别耦合到主从锁存器对的多个复用器，其中第一组复用器具有附加到奇数L1锁存器的输入的相应输出，并且第二组复用器具有它们 相应的输出附加到偶数L1锁存器的输入端口。

公开(公告)号：US07386732B2

公开(公告)日：2008-06-10

申请号：US11381436

申请日：2006-05-03

申请人： Edward E. Kelley ,  Franco Motika ,  Paul V. Motika ,  Eric M. Motika

发明人： Edward E. Kelley ,  Franco Motika ,  Paul V. Motika ,  Eric M. Motika

IPC分类号： H04K1/00 ,  H04L9/00

CPC分类号： G06F21/88 ,  G06F21/31 ,  G07C9/00142

摘要： Logic scan based design and electronic fuse (e-fuse) technology are combined to create a circuit macro function that is integrated in a non-critical area of a processor chip or related circuit to provide a new means of securing electronic systems and devices such as computers, appliances, consumer electronics, automobiles, etc. from theft or unauthorized use. Level sensitive scan design (LSSD) techniques are used in conjunction with e-fuses to inhibit or enable system components and sub-components based upon a pre-initialized configuration which must be enabled by a user via password entry.

摘要翻译： 基于逻辑扫描的设计和电子熔丝（e-fuse）技术被组合以产生集成在处理器芯片或相关电路的非关键区域中的电路宏功能，以提供保护电子系统和设备的新手段，例如 计算机，电器，消费电子，汽车等从盗窃或未经授权的使用。 等级敏感扫描设计（LSSD）技术与电子熔丝一起使用，以根据用户通过密码输入启用的预初始化配置来禁止或启用系统组件和子组件。

公开(公告)号：US20080059857A1

公开(公告)日：2008-03-06

申请号：US11924597

申请日：2007-10-25

申请人： LEENDERT HUISMAN ,  William Huott ,  Maroun Kassab ,  Franco Motika

发明人： LEENDERT HUISMAN ,  William Huott ,  Maroun Kassab ,  Franco Motika

IPC分类号： G01R31/28

CPC分类号： G01R31/318533

摘要： Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.

摘要翻译： 提供了用于隔离扫描链中的缺陷的系统，方法和装置。 本发明包括修改包括在扫描链中的多个锁存器的第一测试模式，在修改的第一测试模式下操作锁存器，以及在第二测试模式下操作包括在扫描链中的多个锁存器。 扫描链中与扫描链相邻并跟随卡纸 - @ - 0或卡住 - - - 1故障的部分扫描链可以存储和/或输出与扫描链的先前部分的输出值相匹配的值， 到了错误。 这些值可以从扫描链中卸载并用于诊断（例如，分离缺陷）缺陷扫描链。 提供了许多其他方面。

公开(公告)号：US20080036486A1

公开(公告)日：2008-02-14

申请号：US11876066

申请日：2007-10-22

申请人： Anne Gattiker ,  David Grosch ,  Marc Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul Zuchowski

发明人： Anne Gattiker ,  David Grosch ,  Marc Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul Zuchowski

IPC分类号： G01R31/26

CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/3008 ,  G01R31/31858

摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

公开(公告)号：US07128273B2

公开(公告)日：2006-10-31

申请号：US10907207

申请日：2005-03-24

申请人： Edward E. Kelley ,  Franco Motika ,  Kim H. Ruffing

发明人： Edward E. Kelley ,  Franco Motika ,  Kim H. Ruffing

IPC分类号： G06K19/06 ,  G06K7/00

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/382 ,  G07F7/0886

摘要： A secure card adapter provides for writing of highly secure, single transaction information on a machine-readable medium of a card structure in accordance with a format that may be downloaded from an external data source. The card structure may be, for example, an existing access authorization card or an existing credit card containing account-specific information which can be read and stored in memory of the secure card adapter. Once such account-specific information is read from an existing access authorization or credit card, secure transaction information can be written, together with the account specific information in accordance with the downloaded format information on another card structure to provide a universal access authorization and/or credit card. Thus the secure card adapter provides an enhanced degree of security through an existing or transitional communication infrastructure.

摘要翻译： 安全卡适配器提供根据可从外部数据源下载的格式在卡结构的机器可读介质上写入高度安全的单个交易信息。 卡结构可以是例如现有的访问授权卡或包含可被读取并存储在安全卡适配器的存储器中的特定于特定信息的现有信用卡。 一旦从现有的访问授权或信用卡读取这样的特定于特定信息的信息，可以根据下载的关于另一个卡结构的格式信息，将帐户特定信息与安全交易信息一起写入以提供通用访问授权和/或 信用卡。 因此，安全卡适配器通过现有或过渡的通信基础设施提供增强的安全性。

公开(公告)号：US20060200410A1

公开(公告)日：2006-09-07

申请号：US10906690

申请日：2005-03-02

申请人： Edward Kelley ,  Franco Motika

发明人： Edward Kelley ,  Franco Motika

IPC分类号： G06Q40/00 ,  G07F19/00 ,  G07D11/00

CPC分类号： G07F19/20 ,  G06Q20/1085 ,  G06Q20/32 ,  G06Q20/4014

摘要： A method, secure cell phone and system for securely accessing an automated banking machine using such secure cell phone. The secure cell phone includes a read only memory device in combination with two linear feedback shift registers for generating a unique security transaction code, which includes a cell phone identification concatenated with two pseudo random codes. The automated banking machine is called from the cell phone. One of the pseudo random codes is input into a software emulation of the cell phone circuitry running on the automated banking machine to generate a computed pseudo random code. This computed code is concatenated the input pseudo random code and a determined cell phone identification to generate a computed transaction code. The automated banking machine is securely accessed using the secure cell phone if the computed transaction code matches the unique security transaction code.

摘要翻译： 一种使用这种安全手机安全访问自动银行机的安全手机和系统的方法。 安全手机包括与两个线性反馈移位寄存器组合的只读存储器装置，用于产生唯一的安全事务代码，其包括与两个伪随机代码连接的蜂窝电话标识符。 自动银行机从手机呼叫。 将伪随机码中的一个输入到在自动银行机上运行的蜂窝电话线路的软件仿真，以生成计算的伪随机码。 该计算的代码将输入的伪随机码和确定的蜂窝电话标识相连，以产生计算的交易代码。 如果计算的交易代码与唯一的安全交易代码相匹配，则使用安全手机安全地访问自动银行机。

公开(公告)号：US20060168455A1

公开(公告)日：2006-07-27

申请号：US10905854

申请日：2005-01-24

申请人： Edward Kelley ,  Franco Motika ,  Tijs Wilbrink

发明人： Edward Kelley ,  Franco Motika ,  Tijs Wilbrink

IPC分类号： H04L9/00

CPC分类号： G06F21/31 ,  G06F21/6209 ,  H04L9/3226

摘要： An enhanced security method is provided for accessing information from a second computer using a password at a first computer. According to such method, a password used for accessing information is inputted to the first computer and stored on the first computer. Thereafter, the stored password is encoded using an encoding algorithm which is system specific to the first computer, and the encoded password is then transmitted to the second computer. The encoded password is used at the second computer to grant or deny access to the requested information, without the second computer having to decode the encoded password to obtain the password stored on the first computer.

摘要翻译： 提供了增强的安全方法，用于在第一计算机处使用密码从第二计算机访问信息。 根据这种方法，将用于访问信息的密码输入到第一计算机并存储在第一计算机上。 此后，使用系统特定于第一计算机的编码算法对存储的密码进行编码，然后将经编码的密码发送到第二计算机。 编码的密码在第二计算机上用于授予或拒绝对所请求的信息的访问，而第二计算机必须对编码密码进行解码以获得存储在第一计算机上的密码。

公开(公告)号：US07076663B2

公开(公告)日：2006-07-11

申请号：US09992893

申请日：2001-11-06

申请人： Edward E. Kelley ,  Franco Motika ,  Paul V. Motika ,  Eric M. Motika

发明人： Edward E. Kelley ,  Franco Motika ,  Paul V. Motika ,  Eric M. Motika

IPC分类号： H04K1/00 ,  H04L9/00

CPC分类号： G06F21/88 ,  G06F21/31 ,  G07C9/00142

摘要： Logic scan based design and electronic fuse (e-fuse) technology are combined to create a circuit macro function that is integrated in a non-critical area of a processor chip or related circuit to provide a new means of securing electronic systems and devices such as computers, appliances, consumer electronics, automobiles, etc. from theft or unauthorized use. Level sensitive scan design (LSSD) techniques are used in conjunction with e-fuses to inhibit or enable system components and sub-components based upon a pre-initialized configuration which must be enabled by a user via password entry.

公开(公告)号：US20060071653A1

公开(公告)日：2006-04-06

申请号：US10539247

申请日：2003-02-20

申请人： Anne Gattiker ,  David Grosch ,  Marc Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul Zuchowski

发明人： Anne Gattiker ,  David Grosch ,  Marc Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul Zuchowski

IPC分类号： G01R19/00

CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/2856 ,  G01R31/3004 ,  G01R31/3008

摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

摘要翻译： 测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。 该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。 此外，这些方法在应力测试期间提供更有效的应力。 该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。 通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。