公开(公告)号：US20070220468A1

公开(公告)日：2007-09-20

申请号：US11752035

申请日：2007-05-22

申请人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

发明人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

摘要翻译： 公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。 最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。 根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。 在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

公开(公告)号：US20060181323A1

公开(公告)日：2006-08-17

申请号：US10906343

申请日：2005-02-15

申请人： Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone

发明人： Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00032

摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.

摘要翻译： 在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。 通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。 将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压 在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

公开(公告)号：US20060101362A1

公开(公告)日：2006-05-11

申请号：US10904397

申请日：2004-11-08

申请人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

发明人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045

摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

摘要翻译： 公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。 最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。 根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。 在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

公开(公告)号：US20050040841A1

公开(公告)日：2005-02-24

申请号：US10604844

申请日：2003-08-21

申请人： Joseph Iadanza

发明人： Joseph Iadanza

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/40 ,  H01L21/822 ,  H01L27/04 ,  G01R31/36

CPC分类号： G01R31/40 ,  G01R31/31721

摘要： A voltage regulated power supply test circuit including: a voltage regulator electrically connected to at least one regulated voltage node of a functional circuit of an integrated circuit chip; and means for selectively connecting between one of the at least one regulated voltage nodes and ground with at least one load circuit adapted to put an emulated current load of the functional circuit on the regulated voltage supply.

摘要翻译： 一种电压调节电源测试电路，包括：电连接到集成电路芯片的功能电路的至少一个调节电压节点的电压调节器; 以及用于选择性地将所述至少一个调节电压节点中的一个与地之间的至少一个负载电路连接的装置，所述负载电路适于将所述功能电路的仿真电流负载置于所述稳压电源上。