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    Damping of LC Ringing in IC (Integrated Circuit) Power Distribution Systems
    1.
    发明申请
    Damping of LC Ringing in IC (Integrated Circuit) Power Distribution Systems 失效
    IC（集成电路）配电系统中LC振荡的阻尼

    公开(公告)号：US20050110551A1

    公开(公告)日：2005-05-26

    申请号：US10707171

    申请日：2003-11-25

    申请人： Anthony Bonaccio ,  Allen Haar ,  Michael Sorna ,  Ivan Wemple ,  Stephen Wyatt

    发明人： Anthony Bonaccio ,  Allen Haar ,  Michael Sorna ,  Ivan Wemple ,  Stephen Wyatt

    IPC分类号： G05F1/10 ,  G05F3/02 ,  H03K17/16 ,  H03L5/00

    CPC分类号： G11C5/14 ,  H01L23/50 ,  H01L2924/0002 ,  H03K17/164 ,  H01L2924/00

    摘要： A structure and method for damping LC (inductance-capacitance) ringing in integrated circuit (IC) power distribution systems. The structure comprises a resistance electrically connected in parallel with a plurality of electrical switches. The resistance and electrical switches are electrically connected in series with the package and on-chip power distribution circuit. When on-chip switching activity creates a sudden and appreciable change in IC power demand the electrical switches are opened to temporarily increase the resistance in series with the power supply. This serves to dampen the power-distribution LC ringing. Later, the electrical switches are closed to shunt the series resistance and reduce the level of steady-state voltage drop in the power structure.

    摘要翻译： 用于阻尼集成电路（IC）配电系统中LC（电感 - 电容）振铃的结构和方法。 该结构包括与多个电开关并联电连接的电阻。 电阻和电气开关与封装和片上配电电路串联电连接。 当片上切换活动产生IC功率需求的突然和明显的变化时，电开关被打开以临时增加与电源串联的电阻。 这用于抑制功率分配LC振铃。 之后，电开关闭合以分流串联电阻并降低电源结构中稳态电压降的水平。

    Method and Apparatus for Converting Globally Clock-Gated Circuits to Locally Clock-Gated Circuits
    2.
    发明申请
    Method and Apparatus for Converting Globally Clock-Gated Circuits to Locally Clock-Gated Circuits 审中-公开
    用于将全局时钟门控电路转换为本地时钟门控电路的方法和装置

    公开(公告)号：US20070220468A1

    公开(公告)日：2007-09-20

    申请号：US11752035

    申请日：2007-05-22

    申请人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

    发明人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

    摘要翻译： 公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。 最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。 根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。 在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

    METHOD AND APPARATUS FOR CONVERTING GLOBALLY CLOCK-GATED CIRCUITS TO LOCALLY CLOCK-GATED CIRCUITS
    3.
    发明申请
    METHOD AND APPARATUS FOR CONVERTING GLOBALLY CLOCK-GATED CIRCUITS TO LOCALLY CLOCK-GATED CIRCUITS 有权
    将全球时钟电路转换到局部时钟电路的方法和装置

    公开(公告)号：US20060101362A1

    公开(公告)日：2006-05-11

    申请号：US10904397

    申请日：2004-11-08

    申请人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

    发明人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5045

    摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

    摘要翻译： 公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。 最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。 根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。 在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

    PSEUDO-RANDOM BINARY SEQUENCE CHECKER WITH AUTOMATIC SYNCHRONIZATION
    4.
    发明申请
    PSEUDO-RANDOM BINARY SEQUENCE CHECKER WITH AUTOMATIC SYNCHRONIZATION 有权
    具有自动同步的PSEUDO随机二进制序列检查器

    公开(公告)号：US20050071399A1

    公开(公告)日：2005-03-31

    申请号：US10605381

    申请日：2003-09-26

    申请人： Anthony Bonaccio ,  Allen Haar

    发明人： Anthony Bonaccio ,  Allen Haar

    IPC分类号： G01R31/317 ,  G01R31/3183 ,  G06F1/02 ,  G06F7/58

    CPC分类号： G01R31/318385 ,  G01R31/31703 ,  G01R31/31728 ,  G06F7/584 ,  G06F2207/582

    摘要： A pseudo-random binary sequence checker having automatic synchronization is disclosed. The pseudo-random binary sequence checker includes a receiver, a synchronizer, and a comparator. The receiver is capable of receiving a pseudo-random binary sequence, which is generated by a pseudo-random binary sequence generator, in a parallel fashion n bits at a time. The synchronizer automatically synchronizes the state of the receiver with an n-bit sample within the pseudo-random binary sequence and calculate all subsequent n-bit sample within the pseudo-random binary sequence. The comparator compares the subsequent calculated n-bit sample within the pseudo-random binary sequence to the next subsequent next received n-bit sample within the pseudo-random binary sequence to indicate an error condition has occurred if each calculated n-bit sample within the pseudo-random binary sequence does not equal to the corresponding received n-bit sample within the pseudo-random binary sequence.

    摘要翻译： 公开了具有自动同步的伪随机二进制序列检验器。 伪随机二进制序列检查器包括接收器，同步器和比较器。 接收机能够以并行方式一次接收由伪随机二进制序列生成器生成的伪随机二进制序列，每个n位。 同步器自动将接收器的状态与伪随机二进制序列内的n位采样同步，并计算伪随机二进制序列内的所有随后的n位采样。 比较器将伪随机二进制序列中随后计算的n位采样与伪随机二进制序列中的下一个接下来的接收到的n位采样进行比较，以指示如果每个计算的n位采样在 伪随机二进制序列不等于伪随机二进制序列内的相应接收的n位样本。

    METHOD AND APPARATUS FOR STORING CIRCUIT CALIBRATION INFORMATION
    5.
    发明申请
    METHOD AND APPARATUS FOR STORING CIRCUIT CALIBRATION INFORMATION 失效
    存储电路校准信息的方法和装置

    公开(公告)号：US20070115019A1

    公开(公告)日：2007-05-24

    申请号：US11164040

    申请日：2005-11-08

    申请人： Anthony Bonaccio ,  Allen Haar ,  Joseph Iadanza ,  Douglas Stout ,  Ivan Wemple

    发明人： Anthony Bonaccio ,  Allen Haar ,  Joseph Iadanza ,  Douglas Stout ,  Ivan Wemple

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2884 ,  G01R35/005

    摘要： A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.

    摘要翻译： 公开了一种用于改变电路特性以使它们与集成电路内的器件的处理参数无关的方法。 通过在晶片上的选择性芯片组上的切口或片上内置测试来测量工艺参数，并将结果存储在每个相应芯片内的存储装置上。 然后，对于剩余的每个芯片，执行二维内插，以基于测量值确定各个芯片的处理参数值。 内插值与芯片在efuse控制文件中的坐标一起被记录。 这样的信息随后被存储在芯片内的efuse模块中。 片上数字控制结构用于根据存储在efuse模块中的信息来调整芯片内的功能组件的某些操作特性。